AD1877
Sample Delay
The sample delay or “group delay” of the AD1877 is dominated
by the processing time of the digital decimation filter. FIR fil-
ters convolve a vector representing time samples of the input
with an equal-sized vector of coefficients. After each convolu-
tion, the input vector is updated by adding a new sample at one
end of the “pipeline” and discarding the oldest input sample at
the other. For an FIR filter, the time at which a step input appears
at the output will be when that step input is half way through
the input sample vector pipeline. The input sample vector
is updated every 64
×
F
S
. The equation which expresses the
group delay for the AD1877 is:
Group Delay
(sec) = 36/F
S
(Hz)
For the most common sample rates this can be summarized as:
F
S
48 kHz
44.1 kHz
32 kHz
Group Delay
750
µs
816
µs
1125
µs
For the AD1877, the input clock operates at either 256
×
F
S
or
384
×
F
S
as selected by the 384/256 pin. When 384/256 is HI,
the 384 mode is selected and when 384/256 is LO, the 256
mode is selected. In both cases, the clock is divided down to
obtain the 64
×
F
S
clock required for the modulator. The out-
put word rate itself will be at F
S
. This relationship is illustrated
for popular sample rates below:
256 Mode
CLKIN
384 Mode
CLKIN
Modulator
Output Word
Sample Rate Rate
48 kHz
44.1 kHz
32 kHz
12.288 MHz 18.432 MHz 3.072 MHz
11.2896 MHz 16.9344 MHz 2.822 MHz
8.192 MHz
12.288 MHz 2.048 MHz
The AD1877 serial interface will support both master and slave
modes. Note that in slave mode it is required that the serial
interface clocks are externally derived from a common source.
In master mode, the serial interface clock outputs are internally
derived from CLKIN.
Reset, Autocalibration and Power Down
Due to the linear phase properties of FIR filters, the group
delay variation, or differences in group delay at different fre-
quencies is essentially zero.
OPERATING FEATURES
Voltage Reference and External Filter Capacitors
The AD1877 includes a +2.25 V on-board reference that deter-
mines the AD1877’s input range. The left and right reference
pins (14 and 15) should be bypassed with a 0.1
µF
ceramic chip
capacitor in parallel with a 4.7
µF
tantalum as shown below in
Figure 3. Note that the chip capacitor should be closest to the
pin. The internal reference can be overpowered by applying an
external reference voltage at the V
REF
L (Pin 14) and V
REF
R
(Pin 15) pins, allowing multiple AD1877s to be calibrated to
the same gain. It is not possible to overpower the left and right
reference pins individually; the external reference voltage
should be applied to both Pin 14 and Pin 15. Note that the ref-
erence pins must still be bypassed as shown in Figure 3.
It is possible to bypass each reference pin (V
REF
L and V
REF
R)
with a capacitor larger than the suggested 4.7
µF,
however it is
not recommended. A larger capacitor will have a longer charge-
up time which may extend into the autocalibration period, yield-
ing incorrect results.
The AD1877 requires four external filter capacitors on Pins 11,
12, 17 and 18. These capacitors are used to filter the single-to
differential converter outputs, and are too large for practical
integration onto the die. They should be 470 pF NPO ceramic
chip type capacitors as shown in Figure 3, placed as close to the
AD1877 package as possible.
Sample Clock
The active LO
RESET
pin (Pin 23) initializes the digital deci-
mation filter and clears the output data buffer. While in the reset
state, all digital pins defined as outputs of the AD1877 are
driven to ground (except for BCLK, which is driven to the state
defined by RDEDGE (Pin 6)). Analog Devices recommends
resetting the AD1877 on initial power up so that the device is
properly calibrated. The reset signal must remain LO for the
minimum period specified in “Specifications” above. The reset
pulse is asynchronous with respect to the master clock, CLKIN.
If, however, multiple AD1877s are used in a system, and it is
desired that they leave the reset state at the same time, the
common reset pulse should be made synchronous to CLKIN
(i.e.,
RESET
should be brought HI on a CLKIN falling edge).
Multiple AD1877s can be synchronized to each other by using
a single master clock and a single reset signal to initialize all
devices. On coming out of reset, all AD1877s will begin sam-
pling at the same time. Note that in slave mode, the AD1877 is
inactive (and all outputs are static, including WCLK) until the
first rising edge of LRCK after the first falling edge of LRCK.
This initial low going then high going edge of LRCK can be used
to “skew” the sampling start-up time of one AD1877 relative to
other AD1877s in a system. In the Data Position Controlled by
WCLK Input mode, WCLK must be HI with LRCK HI, then
WCLK HI with LRCK LO, then WCLK HI with LRCK HI
before the AD1877 starts sampling.
The AD1877 achieves its specified performance without the
need for user trims or adjustments. This is accomplished
through the use of on-chip automatic offset calibration that
takes place immediately following reset. This procedure nulls
out any offsets in the single-to-differential converter, the analog
modulator and the decimation filter. Autocalibration completes
in approximately 8192
×
(1/(F
L
R
CK
) seconds, and need only be
performed once at power-up in most applications. [In slave
mode, the 8192 cycles required for autocalibration do not start
until after the first rising edge of LRCK following the first fall-
ing edge of LRCK.] The autocalibration scheme assumes that
the inputs are ac coupled. DC coupled inputs will work with the
AD1877, but the autocalibration algorithm will yield an incor-
rect offset compensation.
An external master clock supplied to CLKIN (Pin 28) drives
the AD1877 modulator, decimator, and digital interface. As
with any analog-to-digital conversion system, the sampling clock
must be low jitter to prevent conversion errors. If a crystal oscil-
lator is used as the clock source, it should be bypassed with a
0.1
µF
capacitor, as shown below in Figure 3.
REV. A
–7–
AD [ ANALOG DEVICES ]
