AD1877
DIGITAL I/O
Min
Input Voltage HI (V
IH
)
Input Voltage LO (V
IL
)
Input Leakage (I
IH
@ V
IH
= 5 V)
Input Leakage (I
IL
@ V
IL
= 0 V)
Output Voltage HI (V
OH
@ I
OH
= –2 mA)
Output Voltage LO (V
OL
@ I
OL
= 2 mA)
Input Capacitance
2.4
Typ
Max
0.8
10
10
Unit
V
V
µA
µA
V
V
pF
2.4
0.4
15
DIGITAL TIMING
(Guaranteed over 0°C to 70°C, DV
DD
= AV
DD
= 5 V
±
5%. Refer to Figures 17–19.)
Min
t
CLKIN
F
CLKIN
t
CPWL
t
CPWH
t
RPWL
t
BPWL
t
BPWH
t
DLYCKB
t
DLYBLR
t
DLYBWR
t
DLYBWF
t
DLYDT
t
SETLRBS
t
DLYLRDT
t
SETWBS
t
DLYBDT
CLKIN Period
CLKIN Frequency (1/t
CLKIN
)
CLKIN LO Pulsewidth
CLKIN HI Pulsewidth
RESET
LO Pulsewidth
BCLK LO Pulsewidth
BCLK HI Pulsewidth
CLKIN Rise to BCLK Xmit (Master Mode)
BCLK Xmit to LRCK Transition (Master Mode)
BCLK Xmit to WCLK Rise
BCLK Xmit to WCLK Fall
BCLK Xmit to Data/Tag Valid (Master Mode)
LRCK Setup to BCLK Sample (Slave Mode)
LRCK Transition to Data/TAG Valid (Slave Mode)
No MSB Delay Mode (for MSB Only)
WCLK Setup to BCLK Sample (Slave Mode)
Data Position Controlled by WCLK Input Mode
BCLK Xmit to DATA/TAG Valid (Slave Mode)
All Bits Except MSB in No MSB Delay Mode
All Bits in MSB Delay Mode
48
1.28
15
15
50
15
15
Typ
81
12.288
Max
780
20.48
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
10
10
10
10
40
10
10
ns
POWER
Min
Supplies
Voltage, Analog and Digital
Analog Current
Analog Current—Power Down (CLKIN Running)
Digital Current
Digital Current—Power Down (CLKIN Running)
Dissipation
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
Power Down—Both Supplies (CLKIN Running)
Power Down—Both Supplies (CLKIN Not Running)
Power Supply Rejection (See TPC 5)
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
Stopband (≥0.55
×
F
S
)—any 300 mV p-p Signal
4.75
Typ
5
35
6
16
13
255
175
80
95
5
76
71
80
Max
5.25
43
26
20
39
315
215
100
325
Unit
V
mA
µA
mA
µA
mW
mW
mW
µW
µW
dB
dB
dB
REV. A
–3–
AD [ ANALOG DEVICES ]
