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AD1877JR 参数 Datasheet PDF下载

AD1877JR图片预览
型号: AD1877JR
PDF下载: 下载PDF文件 查看货源
内容描述: 单电源, 16位立体声ADC [Single-Supply 16-Bit Stereo ADC]
分类和应用:
文件页数/大小: 18 页 / 254 K
品牌: AD [ ANALOG DEVICES ]
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AD1877
(
Continued from Page 1
)
The flexible serial output port produces data in twos-comple-
ment, MSB-first format. The input and output signals are TTL
compatible. The port is configured by pin selections. Each 16-bit
output word of a stereo pair can be formatted within a 32-bit
field of a 64-bit frame as either right-justified, I
2
S-compatible,
Word Clock controlled or left-justified positions. Both 16-bit
samples can also be packed into a 32-bit frame, in left-justified
and I
2
S-compatible positions.
The AD1877 is fabricated on a single monolithic integrated circuit
using a 0.8
µm
CMOS double polysilicon, double metal process,
and is offered in a plastic 28-lead SOIC package. Analog and
digital supply connections are separated to isolate the analog cir-
cuitry from the digital supply and reduce digital crosstalk.
The AD1877 operates from a single 5 V power supply over the
temperature range of 0°C to 70°C, and typically consumes less
than 260 mW of power.
THEORY OF OPERATION
Modulator Noise-Shaping
offset and indirect dependence on temperature and time as it
affects dc offset. The AD1877 suppresses idle tones 20 dB or
better below the integrated noise floor.
The AD1877’s modulator was designed, simulated, and exhaus-
tively tested to remain stable for any input within a wide tolerance
of its rated input range. The AD1877 is designed to internally
reset itself should it ever be overdriven, to prevent it from going
instable. It will reset itself within 5
µs
at a 48 kHz sampling
frequency after being overdriven. Overdriving the inputs will
produce a waveform “clipped” to plus or minus full scale.
See TPCs 1 through 16 for illustrations of the AD1877’s
typical analog performance as measured by an Audio Precision
System One. Signal-to(distortion + noise) is shown under a
range of conditions. Note that there is a small variance between
the AD1877 analog performance specifications and some of the
performance plots. This is because the Audio Precision System
One measures THD and noise over a 20 Hz to 24 kHz band-
width, while the analog performance is specified over a 20 Hz to
20 kHz bandwidth (i.e., the AD1877 performs slightly better
than the plots indicate). The power supply rejection (TPC 5)
graph illustrates the benefits of the AD1877’s internal differen-
tial architecture. The excellent channel separation shown in
TPC 6 is the result of careful chip design and layout.
Digital Filter Characteristics
The stereo, internally differential analog modulator of the
AD1877 employs a proprietary feedforward and feedback archi-
tecture that passes input signals in the audio band with a unity
transfer function yet simultaneously shapes the quantization
noise generated by the one-bit comparator out of the audio
band. See Figure 1. Without the
∑∆
architecture, this quantiza-
tion noise would be spread uniformly from dc to one-half the
oversampling frequency, 64
×
F
S
.
V
IN
DAC
MODULATOR
BITSTREAM
OUTPUT
V
IN
SINGLE TO
DIFFERENTIAL
CONVERTER
The digital decimator accepts the modulator’s stereo bitstream
and simultaneously performs two operations on it. First, the
decimator low-pass filters the quantization noise that the modu-
lator shaped to high frequencies and filters any other out-of
audio-band input signals. Second, it reduces the data rate to an
output word rate equal to F
S
. The high frequency bitstream is
decimated to stereo 16-bit words at 48 kHz (or other desired
F
S
). The out-of-band one-bit quantization noise and other high
frequency components of the bitstream are attenuated by at
least 90 dB.
The AD1877 decimator implements a symmetric Finite Impulse
Response (FIR) filter which possesses a linear phase response.
This filter achieves a narrow transition band (0.1
×
F
S
), high
stopband attenuation (> 90 dB), and low passband ripple
(< 0.006 dB). The narrow transition band allows the unattenu-
ated digitization of 20 kHz input signals with F
S
as low as
44.1 kHz. The stopband attenuation is sufficient to eliminate
modulator quantization noise from affecting the output. Low
passband ripple prevents the digital filter from coloring the
audio signal. See TPC 7 for the digital filter’s characteristics.
The output from the decimator is available as a single serial
output, multiplexed between left and right channels.
Note that the digital filter itself is operating at 64
×
F
S
. As a
consequence, Nyquist images of the passband, transition band,
and stopband will be repeated in the frequency spectrum at
multiples of 64
×
F
S
. Thus the digital filter will attenuate to
greater than 90 dB across the frequency spectrum except for a
window
±
0.55
×
F
S
wide centered at multiples of 64
×
F
S
. Any
input signals, clock noise, or digital noise in these frequency
windows will not be attenuated to the full 90 dB. If the high
frequency signals or noise appear within the passband images
within these windows, they will not be attenuated at all, and
therefore input antialias filtering should be applied.
DAC
V
IN
Figure 1. Modulator Noise-Shaper (One Channel)
∑∆
architectures “shape” the quantization noise-transfer function
in a nonuniform manner. Through careful design, this transfer
function can be specified to high-pass filter the quantization
noise out of the audio band into higher frequency regions. The
AD1877 also incorporates a feedback resonator from the fourth
integrator’s output to the third integrator’s input. This resonator
does not affect the signal transfer function but allows the flexible
placement of a zero in the noise transfer function for more effec-
tive noise shaping.
Oversampling by 64 simplifies the implementation of a high per-
formance audio analog-to-digital conversion system. Antialias
requirements are minimal; a single pole of filtering will usually
suffice to eliminate inputs near F
S
and its higher multiples.
A fourth-order architecture was chosen both to strongly shape
the noise out of the audio band and to help break up the idle
tones produced in all
∑∆
architectures. These architectures have
a tendency to generate periodic patterns with a constant dc input, a
response that looks like a tone in the frequency domain. These
idle tones have a direct frequency dependence on the input dc
–6–
REV. A