AD1854
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB–1 MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1 MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
Figure 3. Left-Justified Mode
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
Figure 4. 32
×
F
S
Packed Mode
t
CCP
CDATA
D15
t
CHD
D14
D0
CCLK
t
CCH
t
CCL
t
CSU
t
CLL
t
CLH
CLATCH
Figure 5. Serial Control Port Timing
Serial Control Port
The AD1854 serial control port is SPI-compatible. SPI (Serial
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
input mode, soft power-down control, soft de-emphasis, channel-
specific attenuation and mute (both channels at once). The
AD1854 serial control port consists of three signals, control
clock CCLK (Pin 4), control data CDATA (Pin 5), and control
latch CLATCH (Pin 3). The control data input must be valid
on the control clock rising edge, and the control clock must make a
LO to HI transition when there is valid data. The control latch
must make a LO-to-HI transition after the LSB has been clocked
into the AD1854, while the control clock is inactive. The timing
relation between these signals is shown in Figure 5. The control
bits are assigned as in Table IV.
Table III. Digital Timing
The serial control port is byte oriented. The data is MSB first,
and is unsigned. There is one control register for the left
channel or the right channel, as distinguished by Bit Data 10.
For power-up and reset, the default settings are: Data 11 the
mute control bit, reset default state is LO, which is the normal
(nonmuted) setting. Data 10 is LO, the Volume 9 through
Volume 0 control bits have a reset default value of 11 1111 1111,
which is an attenuation of 0.0 dB (i.e., full scale, no attenuation).
The intent with these reset defaults is to enable AD1854 applica-
tions without requiring the use of the serial control port. For those
users who do not use the serial control port, it is still possible to
mute the AD1854 output by using the MUTE (Pin 23) signal.
Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the L/RCLK after the
CLATCH write pulse as shown in Figure 8.
The SPI port can be used in either of two modes, Burst Mode,
or Continuous CCLK Mode, as described below.
Continuous CCLK Mode
Min
t
CCH
t
CCL
t
CCP
t
CSU
t
CHD
t
CLL
t
CLH
CCLK HI Pulsewidth
CCLK LO Pulsewidth
CCLK Period
CDATA Setup Time
CDATA Hold Time
CLATCH LO Pulsewidth
CLATCH HI Pulsewidth
40 (Burst Mode)
40 (Burst Mode)
80 (Burst Mode)
10
10
10
130 (Burst Mode)
Unit
ns
ns
ns
ns
ns
ns
ns
In this mode, the maximum CCLK frequency is 3 MHz. The
CCLK can run continuously between transactions. Please note
that the LO-to-HI transition of the CLATCH with respect to
the rising edge of CCLK must be at least 130 ns, as shown in
Figure 6.
Table IV. Serial Control Bit Definitions
MSB
Data 15 Data 14 Data 13 Data 12
IDPM1
Input
Mode1
Select
IDPM0
Input
Mode0
Select
Soft
Power-
Down
LSB
Data 0
Data 11
Data 10 Data 9
Data 8
Data 7
Data 6
Volume
Control
Data
Data 5
Volume
Control
Data
Data 4
Volume
Control
Data
Data 3
Volume
Control
Data
Data 2
Volume
Control
Data
Data 1
Soft
1/Mute
1/Right
De-
0/Normal 0/Left
Emphasis (Nonmute)
Volume Volume Volume
Control Control Control
Data
Data
Data
Volume Volume
Control Control
Data
Data
REV. A
–7–
AD [ ANALOG DEVICES ]
