AD1854
OPERATING FEATURES
Serial Data Input Port
The AD1854’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The input data
consists of either 16, 18, 20, or 24 bits, as established by the
mode select pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the
mode select bits (Bits 15 and 14) in the control register through
the SPI (Serial Peripheral Interface) control port. Neither the
pins nor the SPI controls has preference; to ensure proper control,
the selection not being used should be tied LO. Therefore,
when the SPI bits are used to control Serial Data Input Format,
Pins 20 and 21 should be tied LO. Similarly, when the pins are
to be used to select the Data Format, the SPI bits should be set
to zeros. When the SPI Control Port is not being used, the SPI
Pins (3, 4, and 5) should be tied LO.
Serial Data Input Mode
Figure 1 shows the right-justified mode (16-bit mode). L/RCLK
is HI for the left channel, LO for the right channel. Data is valid
on the rising edge of BCLK. The MSB is delayed 16-bit clock
periods from an L/RCLK transition, so that when there are 64
BCLK periods per L/RCLK period, the LSB of the data will be
right justified to the next L/RCLK transition. The right-justified
mode can also be used with 20-bit or 24-bit inputs as selected
in Table I.
Figure 2 shows the I
2
S-justified mode. L/RCLK is LO for the
left channel and HI for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left justified to an L/RCLK
transition but with a single BCLK period delay. The I
2
S-justified
mode can be used with 16-/18-/20- or 24-bit inputs.
Figure 3 shows the left-justified mode.
Note: Left-justified mode
is selected by pulsing IDPM1 (Pin 20) with bit clock, that is, tying
bit clock to IDPM1 while IDPM0 (Pin 21) is tied LO. Left-
justified can only be selected this way, it cannot be selected through
SPI Control Port.
L/RCLK is HI for the left channel, and LO for the right channel.
Data is valid on the rising edge of BCLK. The MSB is left-
justified to an L/RCLK transition, with no MSB delay. The
left-justified mode can be used with 16-/18-/20- or 24-bit inputs.
Note that the AD1854 is capable of a 32
×
F
S
BCLK frequency
“packed mode” where the MSB is left-justified to an L/RCLK
transition, and the LSB is right-justified to an L/RCLK transi-
tion. L/RCLK is HI for the left channel, and LO for the right
channel. Data is valid on the rising edge of BCLK. Packed
mode can be used when the AD1854 is programmed in right-
justified mode. Packed mode is shown is Figure 4.
The AD1854 uses two multiplexed input pins to control the
mode configuration of the input data port mode as follows:
Table I. Serial Data Input Modes
IDPM1
(Pin 20)
0
0
1
1
Bit Clock
IDPM0
(Pin 21)
0
1
0
1
0
Serial Data Input Format
Right Justified (16 Bits)
I
2
S-Compatible
Right Justified (20 Bits)
Right Justified (24 Bits)
Left Justified
Table II. Frequency Mode Settings
F
S
Normal, 32 kHz–48 kHz
Normal, 32 kHz–48 kHz
Normal, 32 kHz–48 kHz
Normal, 32 kHz–48 kHz
Double F
S
(96 kHz)
Double F
S
(96 kHz)
Double F
S
(96 kHz)
Double F
S
(96 kHz)
96/48
0
0
0
0
1
1
1
1
MCLK
256
×
F
S
384
×
F
S
512
×
F
S
128
×
F
S
(384/2)
×
F
S
256
×
F
S
X2MCLK
0
0
1
1
0
0
1
1
384/256
0
1
0
1
0
1
0
1
Note
Not Allowed
Not Allowed
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 1. Right-Justified Mode
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB–1 MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
MSB
Figure 2. I
2
S-Justified Mode
–6–
REV. A
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