AD1854
MCLK/SR SELECT
SELECT RATE X2MCLK 384/256 96/48
DVDD
SPDIF
DIRECT
DIRECT
44.1
48.0
96.0
0
0
0
0
0
0
0
0
1
MCLK
11.2896
12.2880
12.2880
MCLK/SR
SEL
JP1
R3
10k
R2
10k
R1
10k
AD1854 STEREO DAC
DVDD
C3
100nF
AVDD
C2
100nF
SDATA
AUDIO
DATA
LRCLK
SCLK
MCLK
OUTPUT BUFFERS AND LP FILTERS
DVDD
96/48
AVDD
OUTL–
C14
1nF, NP0
C13
1nF, NP0
R16
1.96k
R9
2.15k
R8
953
C9
390pF
NP0
R20
549
J1
LEFT
OUT
I/F MODE
RJ, 16-BIT
I
2
S
RJ, 20-BIT
RJ, 24-BIT
LJ
IDPM1 IDPM0
0
0
1
1
BCLK
DVDD
0
1
0
1
0
384/256
X2MCLK
SDATA
OUTL+
L/RCLK
BCLK
R17
1.96k
U3B
R10
953
C10
390pF
NP0
1
53.6k
SSM2135
C15
2.2nF
NP0
I/F
MODE
JP2
R11
2.15k
R4
10k
R5
10k
U1
AD1854JRS
MCLK
IDPM0
IDPM1
R18
1.96k
OUTR–
C17
1nF, NP0
C16
R19 1nF, NP0
1.96k
OUTR+
R15
2.15k
R13
2.15k
R12
953
3RD ORDER LP BESSEL FILTER
CORNER FREQUENCY: 92kHz
GROUP DELAY:
~
2.8 s
DE-EMPHASIS
MUTE
DEEMP
MUTE
CLATCH
CCLK
CCLK
CDATA
CDATA
ZR
ZEROR
ZL
ZEROL
CLATCH
+AV
CC
C11
390pF
NP0
C5
100nF
R21
549
J2
RIGHT
OUT
U3A
R14
953
C12
390pF
NP0
C18
2.2nF
SSM2135
NP0
C6
100nF
53.6k
1
RST
FILTR
FITLB
AGND AGND
C1
100nF
+ C8
– 10 F
+ C7
– 10 F
–AV
EE
PD/RST
DGND
DGND
CDATA
CONTROL
PORT
CCLK
CLATCH
C4
100nF
NOTE:
= DGND
= AGND
ZR
3
ZL
U2A
HC04
1
2
U2B
HC04
4
R6
221
DVDD
CR1
ZERO LEFT
FB1
600Z
CR2
ZERO RIGHT
R7
221
Figure 12. Evaluation Board Circuit
–10–
REV. A
AD [ ANALOG DEVICES ]
