AD7524
WRITE MO D E
CIRCUIT D ESCRIP TIO N
When CS and WR are both LOW, the AD7524 is in the
WRIT E mode, and the AD7524 analog output responds to data
activity at the DB0–DB7 data bus inputs. In this mode, the
AD7524 acts like a nonlatched input D/A converter.
CIRCUIT INFO RMATIO N
T he AD7524, an 8-bit multiplying D/A converter, consists of a
highly stable thin film R-2R ladder and eight N-channel current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.
H O LD MO D E
When either CS or WR is HIGH, the AD7524 is in the HOLD
mode. T he AD7524 analog output holds the value correspond-
ing to the last digital input present at DB0–DB7 prior to WR or
CS assuming the HIGH state.
T he simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT 1 and OUT 2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
MO D E SELECTIO N TABLE
CS
WR
Mode
D AC Response
L
L
Write
DAC responds to data bus
(DB0–DB7) inputs.
H
X
X
H
Hold
Hold
Data bus (DB0–DB7) is
Locked Out:
DAC holds last data present
when WR or CS assumed
HIGH state.
L = Low State, H = High State, X = Don't Care.
WRITE CYCLE TIMING D IAGRAM
Figure 1. Functional Diagram
EQ UIVALENT CIRCUIT ANALYSIS
T he equivalent circuit for all digital inputs LOW is shown in
Figures 2. In Figure 2 with all digital inputs LOW, the refer-
ence current is switched to OUT 2. T he current source ILEAKAGE
is composed of surface and junction leakages to the substrate
1
while the
current source represents a constant 1-bit cur-
256
rent drain through the termination resistor on the R-2R ladder.
T he “ON” capacitance of the output N-channel switches is
120 pF, as shown on the OUT 2 terminal. T he “OFF” switch
capacitance is 30 pF, as shown on the OUT 1 terminal. Analysis
of the circuit for all digital inputs high is similar to Figure 2
however, the “ON” switches are now on terminal OUT 1, hence
the 120 pF appears at that terminal.
Figure 2. AD7524 DAC Equivalent Circuit—All Digital
Inputs Low
INTERFACE LO GIC INFO RMATIO N
MO D E SELECTIO N
AD7524 mode selection is controlled by the CS and WR inputs.
Figure 3. Supply Current vs. Logic Level
T ypical plots of supply current, IDD, versus logic input voltage,
IN, for VDD = +5 V and VDD = +15 V are shown above.
V
–4–
REV. B
ADI [ ADI ]
