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5962-8770003EA 参数 Datasheet PDF下载

5962-8770003EA图片预览
型号: 5962-8770003EA
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS 8位缓冲乘法DAC [CMOS 8-Bit Buffered Multiplying DAC]
分类和应用: 转换器数模转换器
文件页数/大小: 8 页 / 164 K
品牌: ADI [ ADI ]
 浏览型号5962-8770003EA的Datasheet PDF文件第1页浏览型号5962-8770003EA的Datasheet PDF文件第2页浏览型号5962-8770003EA的Datasheet PDF文件第4页浏览型号5962-8770003EA的Datasheet PDF文件第5页浏览型号5962-8770003EA的Datasheet PDF文件第6页浏览型号5962-8770003EA的Datasheet PDF文件第7页浏览型号5962-8770003EA的Datasheet PDF文件第8页  
AD7524  
Power Dissipation (Any Package)  
ABSO LUTE MAXIMUM RATINGS*  
(T A = +25°C, unless otherwise noted)  
T o +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW  
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C  
Operating T emperature  
Commercial (J, K, L) . . . . . . . . . . . . . . . . . –40°C to +85°C  
Industrial (A, B, C) . . . . . . . . . . . . . . . . . . –40°C to +85°C  
Extended (S, T , U) . . . . . . . . . . . . . . . . . –55°C to +125°C  
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C  
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +17 V  
VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V  
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V  
Digital Input Voltage to GND . . . . . . . . –0.3 V to VDD +0.3 V  
OUT 1, OUT 2 to GND . . . . . . . . . . . . . 0.3 V to VDD +0.3 V  
*Stresses above those listed under “Absolute Maximum Ratings” may cause  
permanent damage to the device. T his is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
CAUTIO N  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the AD7524 features proprietary ESD protection circuitry, permanent damage may  
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
with all 1s in the DAC after offset error has been adjusted out  
and is expressed in LSBs. Gain Error is adjustable to zero with  
an external potentiometer.  
TERMINO LO GY  
RELATIVE ACCURACY: A measure of the deviation from a  
straight line through the end points of the DAC transfer function.  
Normally expressed as a percentage of full scale range. For the  
AD7524 DAC, this holds true over the entire VREF range.  
FEED TH RO UGH ERRO R: Error caused by capacitive cou-  
pling from VREF to output with all switches OFF.  
RESO LUTIO N: Value of the LSB. For example, a unipolar con-  
verter with n bits has a resolution of (2–n) (VREF). A bipolar con-  
verter of n bits has a resolution of [2–(n–1)] [VREF]. Resolution in no  
way implies linearity.  
O UTP UT CAP ACITANCE: Capacity from OUT 1 and  
OUT 2 terminals to ground.  
O UTP UT LEAKAGE CURRENT: Current which appears  
on OUT 1 terminal with all digital inputs LOW or on OUT 2  
terminal when all inputs are HIGH. T his is an error current  
which contributes an offset voltage at the amplifier output.  
GAIN ERRO R: Gain Error is a measure of the output error be-  
tween an ideal DAC and the actual device output. It is measured  
P IN CO NFIGURATIO NS  
P LCC  
D IP , SO IC  
LCCC  
REV. B  
–3–