(V = +10 V, VOUT1 = VOUT2 = 0 V, unless otherwise noted)
REF
AD7524–SPECIFICATIONS
1
Lim it, TA = +25؇C
Lim it, T MIN, TMAX
P aram eter
VD D = +5 V VD D = +15 V VD D = 5 V
VD D = +15 V Units
Test Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
8
8
8
8
Bits
Relative Accuracy
J, A, S Versions
K, B, T Versions
L, C, U Versions
Monotonicity
±1/2
±1/2
±1/2
±1/2
±1/4
±1/8
±1/2
±1/2
±1/2
±1/2
±1/4
±1/8
LSB max
LSB max
LSB max
Guaranteed Guaranteed Guaranteed Guaranteed
±2 1/2
±40
Gain Error2
±1 1/4
±10
±3 1/2
±40
±1 1/2
±10
LSB max
ppm/°C
Average Gain T C 3
Gain T C Measured from +25°C to
T MIN or from +25°C to T MAX
% FSR/% max ∆VDD = ±10%
DC Supply Rejection,3 ∆Gain/∆VDD
0.08
0.002
0.02
0.001
0.16
0.01
0.04
0.005
% FSR/% typ
Output Leakage Current
IOUT1 (Pin 1)
IOUT2 (Pin 2)
±50
±50
±50
±50
±400
±400
±200
±200
nA max
nA max
DB0–DB7 = 0 V; WR, CS = 0 V; VREF = ±10 V
DB0–DB7 = VDD; WR, CS = 0 V; VREF = ±10 V
DYNAMIC PERFORMANCE
Output Current Settling Time3
(to 1/2 LSB)
400
250
500
350
ns max
OUT1 Load = 100 Ω, CEXT = 13 pF; WR, CS =
0 V; DB0–DB7 = 0 V to VDD to 0 V.
AC Feedthrough3
at OUT1
at OUT2
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
% FSR max
% FSR max
VREF = ±10 V, 100 kHz Sine Wave; DB0–DB7 =
0 V; WR, CS = 0 V
REFERENCE INPUT
RIN (Pin 15 to GND)4
5
20
5
20
5
20
5
20
kΩ min
kΩ max
ANALOG OUTPUTS
Output Capacitance3
COUT1 (Pin 1)
120
30
30
120
30
30
120
30
30
120
30
30
pF max
pF max
pF max
pF max
DB0–DB7 = VDD; WR, CS = 0 V
DB0–DB7 = 0 V; WR, CS = 0 V
COUT2 (Pin 2)
COUT1 (Pin 1)
COUT2 (Pin 2)
120
120
120
120
DIGITAL INPUTS
Input HIGH Voltage Requirement
VIH
+2.4
+0.8
±1
+13.5
+1.5
±1
+2.4
+0.5
±10
+13.5
+1.5
±10
V min
Input LOW Voltage Requirement
VIL
V max
µA max
Input Current
IIN
VIN = 0 V or VDD
Input Capacitance3
DB0–DB7
WR, CS
5
20
5
20
5
20
5
20
pF max
pF max
VIN = 0 V
VIN = 0 V
SWITCHING CHARACTERISTICS
Chip Select to Write Setup Time5
tCS
See Timing Diagram
tWR = tCS
AD7524J, K, L, A, B, C
AD7524S, T, U
Chip Select to Write Hold Time
tCH
170
170
100
100
220
240
130
150
ns min
ns min
All Grades
0
0
0
0
ns min
Write Pulse Width
tWR
tCS ≥ tWR, tCH ≥ 0
AD7524J, K, L, A, B, C
AD7524S, T, U
Data Setup Time
tDS
170
170
100
100
220
240
130
150
ns min
ns min
AD7524J, K, L, A, B, C
AD7524S, T, U
Data Hold Time
tDH
135
135
60
60
170
170
80
100
ns min
ns min
All Grades
10
10
10
10
ns min
POWER SUPPLY
IDD
1
100
2
100
2
500
2
500
mA max
µA max
All Digital Inputs VIL or VIH
All Digital Inputs 0 V or VDD
NOT ES
1T emperature ranges as follows: J, K, L versions: –40°C to +85°C
A, B, C versions: –40°C to +85°C
S, T , U versions: –55°C to +125°C
2Gain error is measured using internal feedback resistor. Full-Scale Range (FSR) = VREF
3Guaranteed not tested.
.
4DAC thin-film resistor temperature coefficient is approximately –300 ppm/°C.
5AC parameter, sample tested @ +25°C to ensure conformance to specification.
Specifications subject to change without notice
.
–2–
REV. B
ADI [ ADI ]
