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5962-9312601MXA 参数 Datasheet PDF下载

5962-9312601MXA图片预览
型号: 5962-9312601MXA
PDF下载: 下载PDF文件 查看货源
内容描述: [Complete 12-Bit 1.25 MSPS Monolithic A/D Converter]
分类和应用: 信息通信管理转换器
文件页数/大小: 16 页 / 393 K
品牌: ADI [ ADI ]
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AD1671  
(TMIN to TMAX with VCC = +5 V ؎ 5%, VLOGIC = +5 V ؎ 10%, VEE = –5 V ؎ 5%, fSAMPLE = 1 MSPS,  
lNPUT = 1OO kHz, unless otherwise noted)1  
f
AC SPECIFICATIONS  
AD1671J/A/S  
AD1671K  
Typ  
Parameter  
Min  
Typ  
Max  
Min  
Max  
Units  
SIGNAL-TO-NOISE PLUS DISTORTION RATIO  
(S/N + D)  
–0.5 dB Input  
–20 dB Input  
68  
70  
50  
68  
71  
51  
dB  
dB  
EFFECTIVE NUMBER OF BITS (ENOB)  
TOTAL HARMONIC DISTORTION (THD)  
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT  
SMALL SIGNAL BANDWIDTH  
11.2  
11.2  
Bits  
dB  
–80  
–80  
12  
–75  
–77  
–83  
–81  
12  
–75  
–77  
dB  
MHz  
MHz  
FULL POWER BANDWIDTH  
2
2
INTERMODULATION DISTORTION (IMD)2  
2nd Order Products  
3rd Order Products  
–80  
–85  
–75  
–75  
–80  
–85  
–75  
–75  
dB  
dB  
NOTES  
1fIN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a 0 dB ( ±5 V) input signal, unless otherwise  
indicated.  
2fA = 99 kHz, fB = 100 kHz with fSAMPLE = 1 MSPS.  
Specifications subject to change without notice.  
MIN to TMAX with VCC = +5 V ؎ 5%, VLO61C = +5 V ؎ 10%,  
VEE = –5 V ؎ 5%; VIL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)  
SWITCHING SPECIFICATIONS (For all grades T  
Parameters  
Symbol  
Min  
Typ  
Max  
Units  
Conversion Time  
Sample Rate  
tC  
FS  
tENC  
tENCL  
tDAV  
tF  
tR  
tDD  
tSS  
800  
1.25  
50  
ns  
MSPS  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ENCODE Pulse Width High (Figure 1a)  
ENCODE Pulse Width Low (Figure 1b)  
DAV Pulse Width  
ENCODE Falling Edge Delay  
Start New Conversion Delay  
Data and OTR Delay from DAV Falling Edge  
Data and OTR Valid before DAV Rising Edge  
20  
20  
150  
0
0
20  
20  
300  
1
75  
75  
2
NOTES  
1tDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.  
2tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.  
Specifications subject to change without notice.  
tENC  
tC  
ENCODE  
tENCL  
tC  
ENCODE  
tR  
tF  
tDAV  
tR  
DAV  
tDAV  
DAV  
t DD  
tSS  
BIT 1–12  
MSB, OTR  
tDD  
tSS  
DATA 0 (PREVIOUS)  
DATA 1  
BIT 1–12  
MSB, OTR  
DATA 0 (PREVIOUS)  
DATA 1  
Figure 1a. Encode Pulse HIGH  
Figure 1b. Encode Pulse LOW  
REV. B  
–3–