DAC8408
INTERFACE LO GIC SECTIO N
D AC O per ating Modes
• All DACs in HOLD MODE.
• DAC A, B, C, or D individually selected (WRIT E MODE).
• DAC A, B, C, or D individually selected (READ MODE).
• DACs A and C simultaneously selected (WRIT E MODE).
• DACs B and D simultaneously selected (WRIT E MODE).
D AC Selection: Control inputs, DS1, DS2, and A/B select
which DAC can accept data from the input port (see Mode Se-
lection T able).
Mode Selection: Control inputs DS and R/W control the oper-
ating mode of the selected DAC.
Figure 4. Equivalent DAC Circuit (AII Digital Inputs LOW)
Wr ite Mode: When the control inputs DS and R/W are both
low, the selected DAC is in the write mode. T he input data
latches of the selected DAC are transparent, and its analog out-
put responds to activity on the data inputs DB0–DB7.
D IGITAL SECTIO N
Figure 5 shows the digital input/output structure for one bit.
T he digital WR, WR, and RD controls shown in the figure are
internally generated from the external A/B, R/W, DS1, and DS2
signals. T he combination of these signals decide which DAC is
selected. T he digital inputs are CMOS inverters, designed such
that T T L input levels (2.4 V and 0.8 V) are converted into
CMOS logic levels. When the digital input is in the region of 1.2 V
to 1.8 V, the input stages operate in their linear region and draw
current from the +5 V supply (see T ypical Supply Current vs.
Logic Level curve on page 6). It is recommended that the digital
input voltages be as close to VDD and DGND as is practical in
order to minimize supply currents. T his allows maximum sav-
ings in power dissipation inherent with CMOS devices. T he
three-state readback digital output drivers (in the active mode)
provide T T L-compatible digital outputs with a fan-out of one
T T L load. T he three state digital readback leakage-current is
typically 5 nA.
H old Mode: T he selected DAC latch retains the data that was
present on the bus line just prior to DS or R/W going to a high
state. All analog outputs remain at the values corresponding to
the data in their respective latches.
Read Mode: When DS is low and R/W is high, the selected
DAC is in the read mode, and the data held in the appropriate
latch is put back onto the data bus.
MO D E SELECTIO N TABLE
Control Logic
D S1
D S2 A/B
R/W
Mode
D AC
L
L
H
H
H
H
L
L
H
L
H
L
L
L
L
L
WRIT E
WRIT E
WRIT E
WRIT E
A
B
C
D
L
L
H
H
H
H
L
L
H
L
H
L
H
H
H
H
READ
READ
READ
READ
A
B
C
D
L
L
L
L
H
L
L
L
WRIT E
WRIT E
A&C
B&D
H
L
L
H
L
L
X
H
L
X
H
H
HOLD
HOLD
HOLD
A/B/C/D
A/B/C/D
A/B/C/D
Figure 5. Digital Input/Output Structure
L = Low State, H = High State, X = Irrelevant
REV. A
–9–
ADI [ ADI ]
