DAC8408
at V = +5 V; V = ؎10 V; V A, B, C, D = 0 V; T = +25؇C, unless otherwise noted. Specifications apply for
DD
REF
OUT
A
WAFER TESTLIMITS
DAC A, B, C, & D.
D AC8408G
Lim its
P aram eter
Sym bol
Conditions
Units
ST AT IC ACCURACY
Resolution
N
8
Bits min
Nonlinearity1
INL
DNL
GFSE
PSR
±1/2
±1
±1
LSB max
LSB max
LSB max
%FSR/% max
Differential Nonlinearity
Gain Error
Using Internal RFB
Using Internal RFB
Power Supply Rejection
0.001
(∆VDD = ±10%)2
IOUT 1A, B, C, D Leakage Current ILKG
All Digital Inputs = 0 V
±30
nA max
VREF = +10 V
REFERENCE INPUT
Reference Input
RIN
RIN
6/14
kΩ min/max
Resistance3
Input Resistance Match
±1
% max
DIGIT AL INPUT S
Digital Input Low
Digital Input High
Input Current4
VIL
VIH
IIN
0.8
2.4
±1.0
V max
V min
µA max
DAT A BUS OUT PUT S
Digital Output Low
Digital Output High
VOL
VOH
ILKG
1.6 mA Sink
400 µA Source
0.4
4
±1.0
V max
V min
µA max
Output Leakage Current
POWER SUPPLY
Supply Current5
Supply Current6
IDD
IDD
50
1.0
µA max
mA max
NOT ES
1T his is an endpoint linearity specification.
2FSR is Full Scale Range = VREF –1 LSB.
3Input Resistance T emperature Coefficient approximately equals +300 ppm/°C.
4Logic inputs are MOS gates.T ypical input current at +25°C is less than 10 nA.
5All Digital Inputs are either “0” or VDD
.
6All Digital Inputs are either VIH or VIL
.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. A
–5–
ADI [ ADI ]
