DAC8408
Tim ing Diagram
P ARAMETER D EFINITIO NS
RESO LUTIO N
AC FEED TH RO UGH ERRO R
T his is the error caused by capacitance coupling from VREF to
the DAC output with all switches off.
Resolution is the number of states (2n) that the full-scale range
(FSR) of a DAC is divided (or resolved) into.
SETTLING TIME
NO NLINEARITY
Nonlinearity (Relative Accuracy) is a measure of the maximum
deviation from a straight line passing through the end-points of
the DAC transfer function. It is measured after adjusting for
ideal zero and full-scale and is expressed in LSB, %, or ppm of
full-scale range.
Settling T ime is the time required for the output function of the
DAC to settle to within 1/2 LSB for a given digital input signal.
P RO P AGATIO N D ELAY
T his is a measure of the internal delays of the DAC. It is defined
as the time from a digital input change to the analog output cur-
rent reaching 90% of its final value.
D IFFERENTIAL NO NLINEARITY
Differential Nonlinearity is the worst case deviation of any adja-
cent analog outputs from the ideal 1 LSB step size. A specified
differential nonlinearity of ±1 LSB maximum over the operating
temperature range ensures monotonicity.
CH ANNEL-TO -CH ANNEL ISO LATIO N
T his is the portion of input signal that appears at the output of a
DAC from another DAC’s reference input. It is expressed as a
ratio in dB.
GAIN ERRO R
D IGITAL CRO SSTALK
Gain Error (full-scale error) is a measure of the output error be-
tween the ideal and actual DAC output. T he ideal full-scale
output is VREF –1 LSB.
Digital Crosstalk is the glitch energy transferred to the output of
one DAC due to a change in digital input code from other
DACs. It is specified in nVs.
O UTP UT CAP ACITANCE
Output Capacitance is that capacitance between IOUT 1A, IOUT 1B
OUT 1C, or IOUT 1D and AGND.
,
I
REV. A
–7–
ADI [ ADI ]
