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5962-8871902MXA 参数 Datasheet PDF下载

5962-8871902MXA图片预览
型号: 5962-8871902MXA
PDF下载: 下载PDF文件 查看货源
内容描述: 单片12位四路DAC [Monolithic 12-Bit Quad DAC]
分类和应用: 转换器数模转换器信息通信管理
文件页数/大小: 23 页 / 671 K
品牌: ADI [ ADI ]
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AD664  
Figure 12. Preload First Rank Registers  
Load and Update Multiple DAC Outputs  
The following examples demonstrate two ways to update all  
DAC outputs. The first method involves doing all data transfers  
during one long CS low period. Note that in this case, shown in  
Figure 13, LS returns high before CS goes high. Data hold time,  
relative to an address change, is 70 ns. This updates the outputs  
of all DACs simultaneously.  
Figure 10a. Preload First Rank of a DAC  
25؇C  
MIN (ns)  
TMIN to TMAX  
MIN (ns)  
SYMBOL  
tLS  
tLH  
tCW  
tDS  
tDH  
tAS  
tAH  
0
0
15  
80  
0
15  
0
15  
100  
0
15  
0
15  
15  
Figure 10b. Preload First Rank of a DAC Timing  
This allows the user to “preload” the data to a DAC and strobe  
it into the output latch at some future time. The user could do  
this by reproducing the sequence of signals illustrated in the  
next section.  
Figure 13. Update All DAC Outputs  
Update Second Rank of a DAC  
The second method involves doing a CS assertion (low) and an  
LS toggle separately for each DAC. It is basically a series of  
preload operations (Figure 10). In this case, illustrated in Figure  
14, two LS signals are shown. One, labeled LS, goes high before  
CS returns high. This transfers the “new” input word to the  
DAC outputs sequentially. The second LS signal, labeled Alter-  
nate LS, stays low until CS returns high. Using this sequence  
loads the first ranks with each “new” input word but doesn’t up-  
date the DAC outputs. To then update all DAC outputs simul-  
taneously would require the signals illustrated in Figure 11.  
Assuming that a new input code had previously been placed into  
the first rank of the input latches, the user can update the out-  
put of the DAC by simply pulling CS low while keeping LS,  
MS, TR, RD and RST high. Address data is not needed in this  
case. In reality, all second ranks are being updated by this pro-  
cedure, but only those which receive data different from that  
already there would manifest a change. Updating the second  
rank does not change the contents of the first rank.  
Figure 11. Update Second Rank of a DAC  
The same options that exist for individual DAC input loading  
also exist for multiple DAC input loading. That is, the user can  
choose to update the first and second ranks of the registers or  
preload the first ranks and then update them at a future time.  
Figure 14. Load and Update Multiple DACs  
Preload Multiple First Rank Registers  
SELECTING GAIN RANGE AND MODES (44-PIN  
VERSIONS)  
The first ranks of the DAC input registers may be preloaded  
with new input data without disturbing the second rank data.  
This is done by transferring the data into the first rank by bring-  
ing CS low while LS is low. But CS must return high before LS.  
This prevents the data from the first rank from getting into the  
second rank. A simple second rank update cycle as shown in  
Figure 11 would move the “preloaded” information to the  
DACs.  
The AD664’s mode select feature allows a user to configure the  
gain ranges and output modes of each of the four DACs.  
On-board switches take the place of up to eight external relays  
that would normally be required to accomplish this task. The  
switches are programmed by the mode select word entered via  
the data I/O port. The mode select word is eight-bits wide and  
D
REV.  
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