AD664
Fully transparent operation can be thought of as a simultaneous
load of data from Figure 9a where replacing LS with TR causes
all 4 DACs to be loaded at once.
OUTPUT DATA
Two types of outputs may be obtained from the internal data
registers of the AD664 chip, mode select and DAC input code
data. Readback data may be in the same forms in which it can
be entered; 4-, 8-, and 12-bit wide words (12 bits only for
28-pin versions).
The Fully transparent mode is achieved by asserting lows on
QS0, QS1, QS2, TR and CS while keeping LS high in addition
to MS and RB. Figure 18a illustrates the necessary timing rela-
tionships. Fully transparent operation will also work with TR
tied low (enabled).
DAC Data Readback
DAC input code readback data is obtained by setting the address
of the DAC (DS0, DS1) and Quads (QS0, QS1, QS2) on the
address pins and bringing the RD and CS pins low. The timing
diagram for a DAC code readback operation appears in Figure 20.
1
LS
DATA INPUT/
DATA VALID
OUTPUT BITS
tDH
tQH
tDS
QS
TR
CS
tQS
tTW
tTS
tCH
Figure 18a. Fully Transparent Mode
25؇C
MIN (ns)
TMIN to TMAX
MIN (ns)
SYMBOL
tAS
tQS
0
0
0
0
0
0
Figure 20a. DAC Input Code Readback
tTS
*
tTW
tCH
tDH
tQH
80
90
0
90
110
0
25°C
MIN (ns)
TMIN to TMAX
MIN (ns)
SYMBOL
tAS
tRS
tDV
tDF
tAH
tRH
0
0
150
60
0
0
0
180
75
0
0
0
*FOR tTS > 0, THE WIDTH OF TR MUST BE
INCREASED BY THE SAME AMOUNT THAT
tTS IS GREATER THAN 0 ns.
Figure 18b. Fully Transparent Mode Timing
0
0
Partially transparent operation can be thought of as preloading
the first rank in Figure 10a without requiring the additional CS
pulse from Figure 11.
Figure 20b. DAC Input Code Readback Timing
Mode Data Readback
Mode data is read back in a similar fashion. By settingMS, QS0,
QS1, RD and CS low while setting TR and RST high, the mode
select word is presented to the I/O port pins. Figure 21 shows the
timing diagram for a readback of the mode select data register.
The partially transparent mode is achieved by setting CS, QS0,
QS1, QS2, LS, and TR low while keeping RD and MS high.
The address of the transparent DAC is asserted on DS0 and
DS1. Figure 19a illustrates the necessary timing relationships.
Partially transparent operation will also work with TR tied low
(enabled).
DATA INPUT/
DATA VALID
OUTPUT BITS
tDH
tDS
ADDRESS
QS0, QS1, QS2
DS0, DS1, LS
ADDRESS VALID
tAH
tAS
tTS
TR
tTH
tW
CS
Figure 21a. Mode Data Readback
Figure 19a. Partially Transparent
25؇C
MIN (ns)
TMIN to TMAX
MIN (ns)
25°C
MIN (ns)
TMIN to TMAX
MIN (ns)
SYMBOL
SYMBOL
tDS
tAS
tTS
tW
tDH
tAH
tTH
0
0
0
90
15
15
15
0
0
0
110
15
15
15
tAS
tMS
tDV
tDF
tAH
tMH
0
0
150
60
0
0
0
180
75
0
0
0
Figure 21b. DAC Mode Readback Timing
Figure 19b. Partially Transparent Mode Timing
D
REV.
–11–
ADI [ ADI ]
