AD667
The AD667 data and control inputs will float to a Logic 0 if left
open. It is recommended that any unused inputs be connected
to power ground to improve noise immunity.
Fanout for the AD667 is 100 when used with a standard low
power Schottky gate output device.
8-BIT MICROPROCESSOR INTERFACE
The AD667 interfaces easily to 8-bit microprocessor systems of
all types. The control logic makes possible the use of right- or
left-justified data formats.
Whenever a 12-bit DAC is loaded from an 8-bit bus, two bytes
are required. If the program considers the data to be a 12-bit
binary fraction (between 0 and 4095/4096), the data is left-
justified, with the eight most significant bits in one byte and the
remaining bits in the upper half of another byte. Right-justified
data calls for the eight least significant bits to occupy one byte,
with the 4 most significant bits residing in the lower half of an-
other byte, simplifying integer arithmetic.
Figure 5. AD667 Block Diagram
It is permissible to enable more than one of the latches simulta-
neously. If a first rank latch is enabled coincident with the sec-
ond rank latch, the data will reach the second rank correctly if
the “WRITE CYCLE #1” timing specifications are met.
Table II. AD667 Truth Table
CS A3 A2 A1 A0 Operation
1
X
0
0
0
0
0
X
1
1
1
1
0
0
X
1
X
1
X
1
No Operation
No Operation
1
1
0
1
0
1
0
1
1
0
0
1
1
1
0
Enable 4 LSBs of First Rank
Enable 4 Middle Bits of First Rank
Enable 4 MSBs of First Rank
Loads Second Rank from First Rank
All Latches Transparent
“X” = Don’t Care.
Figure 7. 12-Bit Data Formats for 8-Bit Systems
INPUT CODING
Figure 8 shows an addressing scheme for use with an AD667 set
up for left-justified data in an 8-bit system. The base address is
decoded from the high-order address bits and the resultant
active-low signal is applied to CS. The two LSBs of the address
bus are connected as shown to the AD667 address inputs. The
latches now reside in two consecutive locations, with location
X01 loading the four LSBs and location X10 loading the eight
MSBs and updating the output.
The AD667 uses positive-true binary input coding. Logic “1” is
represented by an input voltage greater than 2.0 V and Logic
“0” is defined as an input voltage less than 0.8 V.
Unipolar coding is straight binary, where all zeroes (000H) on
the data inputs yields a zero analog output and all ones (FFFH)
yields an analog output 1 LSB below full scale.
Bipolar coding is offset binary, where an input code of 000H
yields a minus full-scale output, an input of FFFH yields an out-
put 1 LSB below positive full scale, and zero occurs for an input
code with only the MSB on (800H).
The AD667 can be used with twos complement input coding if
an inverter is used on the MSB (DB11).
DIGITAL INPUT CONSIDERATIONS
The threshold of the digital input circuitry is set at 1.4 volts and
does not vary with supply voltage. The input lines can thus in-
terface with any type of 5 volt logic. The configuration of the in-
put circuit is shown in Figure 6.
Figure 8. Left-Justified 8-Bit Bus Interface
Figure 6. Equivalent Digital Input Circuit
REV. A
–7–
ADI [ ADI ]
