AD667
Model
AD667A
Typ
AD667B
Typ
AD667S
Typ
Min
Max
Min
Max
Min
Max
Units
DIGITAL INPUTS
Resolution
Logic Levels (TTL, Compatible, TMIN–TMAX
12
12
12
Bits
1
)
VIH (Logic “l’’)
VIL (Logic “0”)
IIH (VIH = 5.5 V)
IIL (VIL = 0.8 V)
+2.0
0
+5.5
+0.8
10
+2.0
0
+5.5
+0.8
10
+2.0
0
+5.5
+0.7
10
V
V
µA
µA
3
1
3
1
3
1
5
5
5
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ +25°C
TA = TMIN to TMAX
+1/4
±1/2
±1/2
؎1/2
؎3/4
؎3/4
±1/8
±1/4
±1/4
؎1/4
؎1/2
؎1/2
±1/8
±1/8
±1/4
؎1/2
؎3/4
؎3/4
LSB
LSB
LSB
Differential Linearity Error @ +25°C
TA = TMIN to TMAX
Monotonicity Guaranteed Monotonicity Guaranteed
Monotonicity Guaranteed
LSB
Gain Error2
±0.1
±1
±0.05
؎0.2
؎2
؎0.1
±0.1
±1
±0.05
؎0.2
؎2
؎0.1
±0.1
±1
±0.05
؎0.2
؎2
؎0.1
% FSR3
LSB
Unipolar Offset Error2
Bipolar Zero2
% of FSR
DRIFT
Differential Linearity
±2
±5
±1
±5
±2
±5
±2
±15
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
Gain (Full Scale) TA = 25°C to TMIN or TMAX
Unipolar Offset TA = 25°C to TMIN or TMAX
Bipolar Zero TA = 25°C to TMIN or TMAX
± 30
± 3
±10
±15
± 3
±10
؎30
؎3
؎10
CONVERSION SPEED
Settling Time to ±0.01% of FSR for
FSR Change (2 kΩʈ500 pF Load)
with 10 kΩ Feedback
with 5 kΩ Feedback
3
2
1
4
3
3
2
1
4
3
3
2
1
4
3
µs
µs
µs
For LSB Change
Slew Rate
10
10
10
V/µs
ANALOG OUTPUT
Ranges4
±2.5, ±5, ±10,
±2.5, ±5, ±10,
±2.5, ±5, ±10,
V
+5, +10
+5, +10
+5, +10
Output Current
Output Impedance (DC)
Short Circuit Current
±5
±5
±5
mA
Ω
mA
0.05
0.05
0.05
40
40
40
REFERENCE OUTPUT
External Current
9.90
0.1
10.00
1.0
10.10
9.90
0.1
10.00
1.0
10.10
9.90
1.0
10.00
10.10
V
mA
POWER SUPPLY SENSITIVITY
VCC = +11.4 V to +16.5 V dc
5
5
10
10
5
5
10
10
5
5
10
10
ppm of FS/%
ppm of FS/%
VEE = –11.4 V to –16.5 V dc
POWER SUPPLY REQUIREMENTS
Rated Voltages
±12, ±15
±12, ±15
±12, ±15
V
V
Range4
؎11.4
؎16.5
؎11.4
؎16.5
؎11.4
؎16.5
Supply Current
+11.4 V to +16.5 V dc
–11.4 V to –16.5 V dc
8
20
12
25
8
20
12
25
8
20
12
25
mA
mA
TEMPERATURE RANGE
Specification
–25
–65
+85
–25
–65
+85
–55
–65
+125
+150
°C
°C
Storage
+150
+150
TIMING DIAGRAMS
WRITE CYCLE #1
(Load First Rank from Data Bus; A3 = 1)
WRITE CYCLE #2
(Load Second Rank from First Rank; A2, A1, A0 = 1)
REV. A
–3–
ADI [ ADI ]
