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5962-8865901XA 参数 Datasheet PDF下载

5962-8865901XA图片预览
型号: 5962-8865901XA
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor-Compatible 12-Bit D/A Converter]
分类和应用: 转换器
文件页数/大小: 8 页 / 325 K
品牌: ADI [ ADI ]
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AD667–SPECIFICATIONS (@ TA = +25؇C, ؎12 V, ؎15 V power supplies unless otherwise noted)  
Model  
AD667J  
Typ  
AD667K  
Typ  
Min  
Max  
Min  
Max  
Units  
DIGITAL INPUTS  
Resolution  
Logic Levels (TTL, Compatible, TMIN–TMAX  
VIH (Logic “l’’)  
VIL (Logic “0”)  
IIH (VIH = 5.5 V)  
12  
12  
Bits  
1
)
+2.0  
0
+5.5  
+0.8  
10  
+2.0  
0
+5.5  
+0.8  
10  
V
V
µA  
µA  
3
1
3
1
IIL (VIL = 0.8 V)  
5
5
TRANSFER CHARACTERISTICS  
ACCURACY  
Linearity Error @ +25°C  
TA = TMIN to TMAX  
+1/4  
±1/2  
±1/2  
؎1/2  
؎3/4  
؎3/4  
±1/8  
±1/4  
±1/4  
؎1/4  
؎1/2  
؎1/2  
LSB  
LSB  
LSB  
Differential Linearity Error @ +25°C  
TA = TMIN to TMAX  
Monotonicity Guaranteed  
Monotonicity Guaranteed  
LSB  
Gain Error2  
±0.1  
±1  
±0.05  
؎0.2  
؎2  
؎0.1  
±0.1  
±1  
±0.05  
؎0.2  
؎2  
؎0.1  
% FSR3  
LSB  
Unipolar Offset Error2  
Bipolar Zero2  
% of FSR  
DRIFT  
Differential Linearity  
±2  
±5  
±1  
±5  
±2  
±5  
ppm of FSR/°C  
ppm of FSR/°C  
ppm of FSR/°C  
ppm of FSR/°C  
Gain (Full Scale) TA = 25°C to TMIN or TMAX  
Unipolar Offset TA = –25°C to TMIN or TMAX  
Bipolar Zero TA = 25°C to TMIN or TMAX  
±30  
±3  
±10  
±15  
±3  
±10  
CONVERSION SPEED  
Settling Time to ±0.01% of FSR for  
FSR Change (2 kʈ500 pF Load)  
with 10 kFeedback  
with 5 kFeedback  
3
2
1
4
3
3
2
1
4
3
µs  
µs  
µs  
For LSB Change  
Slew Rate  
10  
10  
V/µs  
ANALOG OUTPUT  
Ranges4  
±2.5, ±5, ±10,  
±2.5, ±5, ±10,  
V
+5, +10  
+5, +10  
Output Current  
Output Impedance (DC)  
Short Circuit Current  
±5  
±5  
mA  
mA  
0.05  
0.05  
40  
40  
REFERENCE OUTPUT  
External Current  
9.90  
0.1  
10.00  
1.0  
10.10  
9.90  
0.1  
10.00  
1.0  
10.10  
V
mA  
POWER SUPPLY SENSITIVITY  
VCC = +11.4 V to +16.5 V dc  
5
5
10  
10  
5
5
10  
10  
ppm of FS/%  
ppm of FS/%  
VEE = –11.4 V to –16.5 V dc  
POWER SUPPLY REQUIREMENTS  
Rated Voltages  
±12, ±15  
±12, ±15  
V
V
Range4  
؎11.4  
؎16.5  
؎11.4  
؎16.5  
Supply Current  
+11.4 V to +16.5 V dc  
–11.4 V to –16.5 V dc  
8
20  
12  
25  
8
20  
12  
25  
mA  
mA  
TEMPERATURE RANGE  
Specification  
0
+70  
0
+70  
°C  
°C  
Storage  
–65  
+125  
–65  
+125  
NOTES  
1The digital input specifications are 100% tested at +25°C, and guaranteed but not tested over the full temperature range.  
2Adjustable to zero.  
3FSR means “Full-Scale Range” and is 20 V for ±10 V range and 10 V for the ±5 V range.  
4A minimum power supply of ±12.5 V is required for a ±10 V full-scale output and ±11.4 V is required for all other voltage ranges.  
Specifications subject to change without notice.  
ABSOLUTE MAXIMUM RATINGS  
VCC to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V  
EE to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V  
Specifications shown in boldface are tested on all production units at final electrical  
test. Results from those tests are used to calculate outgoing quality levels. All min and  
max specifications are guaranteed, although only those shown in boldface are tested  
on all production units.  
V
Digital Inputs (Pins 11–15, 17–28)  
to Power Ground . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V  
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . . ±12 V  
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . . ±12 V  
10 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ±12 V  
20 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ±24 V  
Ref Out, VOUT (Pins 6, 9) . . Indefinite Short to Power Ground  
. . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VCC  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW  
TIMING SPECIFICATIONS  
(All Models, TA = +25°C, VCC = +12 V or +15 V, VEE = –12 V or –15 V)  
Symbol Parameter  
Min  
Typ Max  
tDC  
tAC  
tCP  
Data Valid to End of CS  
Address Valid to End of CS  
CS Pulse Width  
50  
100  
100  
0
_
2
_
4
ns  
ns  
ns  
ns  
µs  
tDH  
Data Hold Time  
tSETT  
Output Voltage Settling Time  
–2–  
REV. A