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5962-0150601HXA 参数 Datasheet PDF下载

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型号: 5962-0150601HXA
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道, 14位, 65 MSPS A / D转换器的模拟输入信号调理 [Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning]
分类和应用: 转换器
文件页数/大小: 20 页 / 1431 K
品牌: ADI [ ADI ]
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AD13465  
DEFINITION OF SPECIFICATIONS  
Analog Bandwidth  
The analog input frequency at which the spectral power of the  
fundamental frequency (as determined by the FFT analysis) is  
reduced by 3 dB.  
Minimum Conversion Rate  
The encode rate at which the SNR of the lowest analog signal  
frequency drops by no more than 3 dB below the guaranteed limit.  
Maximum Conversion Rate  
The encode rate at which parametric testing is performed.  
Aperture Delay  
Output Propagation Delay  
The delay between a differential crossing of ENCODE and  
ENCODE command and the instant at which the analog input  
is sampled.  
The delay between a differential crossing of ENCODE and  
ENCODE command and the time when all output data bits are  
within valid logic levels.  
Aperture Uncertainty (Jitter)  
The sample-to-sample variation in aperture delay.  
Overvoltage Recovery Time  
The amount of time required for the converter to recover to  
0.02% accuracy after an analog input signal of the specified  
percentage of full scale is reduced to midscale.  
Differential Analog Input Resistance, Differential Analog  
Input Capacitance, and Differential Analog Input Impedance  
The real and complex impedances measured at each analog  
input port. The resistance is measured statically and the capaci-  
tance and differential input impedances are measured with a  
network analyzer.  
Power Supply Rejection Ratio  
The ratio of a change in input offset voltage to a change in  
power supply voltage.  
Signal-to-Noise-and-Distortion (SINAD)  
Differential Analog Input Voltage Range  
The ratio of the rms signal amplitude (set at 1 dB below full  
scale) to the rms value of the sum of all other spectral compo-  
nents, including harmonics but excluding dc. May be reported  
in dB (i.e., degrades as signal level is lowered) or in dBFS  
(always related back to converter full scale).  
The peak-to-peak differential voltage that must be applied to  
the converter to generate a full-scale response. Peak differential  
voltage is computed by observing the voltage from the other pin,  
which is 180 degrees out of phase. Peak-to-peak differential is  
computed by rotating the inputs phase 180 degrees and taking  
the peak measurement again. The difference is then computed  
between both peak measurements.  
Signal-to-Noise Ratio (without Harmonics)  
The ratio of the rms signal amplitude (set at 1 dB below full scale)  
to the rms value of the sum of all other spectral components,  
excluding the first five harmonics and dc. May be reported in  
dB (i.e., degrades as signal level is lowered) or in dBFS (always  
related back to converter full scale).  
Differential Nonlinearity  
The deviation of any code from an ideal 1 LSB step.  
Encode Pulsewidth/Duty Cycle  
Pulsewidth high is the minimum amount of time that the  
ENCODE pulse should be left in Logic 1 state to achieve rated  
performance; pulsewidth low is the minimum time ENCODE  
pulse should be left in low state. At a given clock rate, these  
specs define an acceptable encode duty cycle.  
Spurious-Free Dynamic Range  
The ratio of the rms signal amplitude to the rms value of the  
peak spurious spectral component. The peak spurious compo-  
nent may or may not be a harmonic.  
Transient Response  
Harmonic Distortion  
The time required for the converter to achieve 0.02% accu-  
racy when a one-half full-scale step function is applied to the  
analog input.  
The ratio of the rms signal amplitude to the rms value of the  
worst harmonic component.  
Integral Nonlinearity  
Two-Tone Intermodulation Distortion Rejection  
The ratio of the rms value of either input tone to the rms value  
of the worst third order intermodulation product; reported in dBc.  
The deviation of the transfer function from a reference line  
measured in fractions of 1 LSB using a “best straight line”  
determined by a least square curve fit.  
tA  
N+3  
N
A
IN  
N+1  
N+2  
N+4  
tENC  
tENCH  
N+1  
tENCL  
ENC, ENC  
N
N+2  
tE_DR  
N+3  
N+4  
tOD  
N3  
N2  
N1  
N
D[13:0]  
DRY  
Figure 1. Timing Diagram  
–8–  
REV. 0