AD13465
or AMP-IN-B-1 when an input of 5 V full scale is desired. Use
AMP-IN-A-2 or AMP-IN-B-2 when 1 V full scale is desired.
Each channel has an AMP-OUT that must be tied to either a
noninverting or inverting input of a differential amplifier with
the remaining input grounded. For example, Side A, AMP-
OUT-A (Pin 6) must be tied to A+IN (Pin 5) with A–IN (Pin 4)
tied to ground for noninverting operation or AMP-OUT-A (Pin 6)
tied to A–IN (Pin 4) with A+IN (Pin 5) tied to ground for
inverting operation.
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter perfor-
mance is the MC100LVEL16 (or same family) from Motorola.
VT
0.1F
ENCODE
ECL/
PECL
AD13465
0.1F
ENCODE
USING THE DIFFERENTIAL INPUT
Each channel of the AD13465 was designed with two optional
differential inputs, A+IN, A–IN and B+IN, B–IN. The inputs
provide system designers with the ability to bypass the AD8037
amplifier and drive the AD8138 directly. The AD8138 differen-
tial ADC driver can be deployed in either a single-ended or
differential input configuration. The differential analog inputs
have a nominal input impedance of 620 Ω and nominal full-
scale input range of 1.2 V p-p. The AD8138 amplifier drives a
differential filter and the custom analog-to-digital converter. The
differential input configuration provides the lowest even-order
harmonics and signal-to-noise (SNR) performance improve-
ment of up to 3 dB (SNR = 73 dBFS). Exceptional care was taken
in the layout of the differential input signal paths. The differen-
tial input transmission line characteristics are matched and
balanced. Equal attention to system level signal paths must be
provided in order to realize significant performance improvements.
VT
Figure 7. Differential ECL for Encode
Jitter Consideration
The signal-to-noise ratio (SNR) for any ADC can be predicted.
When normalized to ADC codes, the equation below, accurately
predicts the SNR based on three terms. These are jitter, average
DNL error, and thermal noise. Each of these terms contributes
to the noise within the converter.
1/2
2
(1+ ε
VNOISE
RMS
SNR = –20 × log
+(2 × π × fANALOG × tJ RMS)2 +
2N
2N
fANALOG
tJ RMS
= analog input frequency
= rms jitter of the encode (rms sum of encode
source and internal encode circuitry)
ε
= average DNL of the ADC (typically 0.50 LSB)
= Number of bits in the ADC
APPLYING THE AD13465
Encoding the AD13465
N
The AD13465 encode signal must be a high quality, extremely
low phase noise source, to prevent degradation of performance.
Maintaining 14-bit accuracy at 65 MSPS places a premium on
encode clock phase noise. SNR performance can easily degrade
3 dB to 4 dB with 32 MHz input signals when using a high-jitter
clock source. See Analog Devices’ Application Note AN-501,
“Aperture Uncertainty and ADC System Performance,” for
complete details. For optimum performance, the AD13465
must be clocked differentially. The encode signal is usually
ac-coupled into the ENCODE and ENCODE pins via a trans-
former or capacitors. These pins are biased internally and require
no additional bias.
VNOISE RMS = V rms noise referred to the analog input of the
ADC (typically 5 LSB)
For a 14-bit analog-to-digital converter like the AD13465, aper-
ture jitter can greatly affect the SNR performance as the analog
frequency is increased. The chart below shows a family of curves
that demonstrates the expected SNR performance of the AD13465
as jitter increases. The chart is derived from the above equation.
For a complete discussion of aperture jitter, please consult Ana-
log Devices’ Application Note AN-501, “Aperture Uncertainty
and ADC System Performance.”
71
70
Shown below is one preferred method for clocking the AD13465.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD13465 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD13465, and limits the
noise presented to the ENCODE inputs. A crystal clock oscillator
can also be used to drive the RF transformer if an appropriate
limited resistor (typically 100 Ω) is placed in the series with
the primary.
A
= 5MHz
IN
69
68
67
66
65
64
A
= 9.9MHz
= 21MHz
IN
A
IN
63
62
61
A
= 32MHz
IN
60
59
58
0.1mF
⍀
100
T1-4T
CLOCK
SOURCE
ENCODE
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.0
AD13465
ENCODE
CLOCK JITTER – ps
HSMS2812
DIODES
Figure 8. SNR vs. Jitter
Figure 6. Crystal Clock Oscillator—Differential Encode
–10–
REV. 0
ADI [ ADI ]
