AD13465
Power Supplies
LAYOUT INFORMATION
Care should be taken when selecting a power source. Linear
supplies are strongly recommended. Switching supplies tend to
have radiated components that may be received by the AD13465.
Each of the power supply pins should be decoupled as closely to
the package as possible, using 0.1 µF chip capacitors.
The schematic of the evaluation board (Figure 10) represents a
typical implementation of the AD13465. The pinout of the
AD13465 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design
practices. It is recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high quality ceramic
chip capacitors.
The AD13465 has separate digital and analog power supply pins.
The analog supplies are denoted AVCC and the digital supply
pins are denoted DVCC. AVCC and DVCC should be separate
power supplies. This is because the fast digital output swings
can couple switching current back into the analog supplies.
Note that AVCC must be held within +5% and –3% of 5 V. The
AD13465 is specified for DVCC = 3.3 V as this is a common
supply for digital ASICs.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.
Output Loading
Care must be taken when designing the data receivers for the
AD13465. The digital outputs drive an internal series resistor
(e.g., 100 Ω) followed by a gate like 75LCX574. To minimize
capacitive loading, there should be only one gate on each output
pin. An example of this is shown in the evaluation board sche-
matic shown in Figure 10. The digital outputs of the AD13465
have a constant output slew rate of 1 V/ns. A typical CMOS
gate combined with a PCB trace will have a load of approximately
10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns)
of dynamic current per bit will flow in or out of the device. A full-
scale transition can cause up to 140 mA (14 bits × 10 mA/bit)
of transient current through the output stages. These switch-
ing currents are confined between ground and the DVCC pin.
Standard TTL gates should be avoided since they can apprecia-
bly add to the dynamic switching currents of the AD13465. It
should also be noted that extra capacitive loading will increase
output timing and invalidate timing specifications. Digital out-
put timing is guaranteed with 10 pF loads.
EVALUATION BOARD
The AD13465 evaluation board (Figure 9) is designed to
provide optimal performance for evaluation of the AD13465
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD13465. The board requires an analog input signal, encode
clock, and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and
the analog section of the AD13465. The digital outputs of the
AD13465 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
Figure 9. Evaluation Board Mechanical Layout
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ADI [ ADI ]
