ACT8846
Rev 4, 25-May-16
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
PB
PB
0xC0
0xC0
[5:2]
1
-
R
Reserved.
Watchdog Soft-Reset Enable. Set this bit to 1 to enable
watchdog function. When the watchdog timer expires, the PMU
commences a soft-reset routine. This bit is automatically reset to
0 when entering sleep mode.
WDSREN
R/W
Watchdog Power-Cycle Enable. Set this bit to 1 to enable
watchdog function. When watchdog timer expires, the PMU
commence a power cycle. This bit is automatically reset to 0
when entering sleep mode.
PB
PB
0xC0
0xC1
0
WDPCEN
INTADR
R/W
R
Interrupt Address. It holds the address of the block that triggers
the interrupt. This byte defaults to 0xFF and is automatically set
to 0xFF after being read. Bit 7 is the MSB while Bit 0 is the LSB.
[7:0]
nPBIN Assertion Interrupt Status. The value of this bit is 1 if the
nPBIN Assertion Interrupt is triggered.
PB
PB
0xC2
0xC2
7
6
PBASTAT
PBDSTAT
R
R
nPBIN De-assertion Interrupt Status. The value of this bit is 1 if
the nPBIN De-assertion Interrupt is triggered.
nPBIN Status bit. This bit contains the real-time status of the
nPBIN pin. The value of this bit is 1 if nPBIN is asserted, and is 0
if nPBIN is de-asserted.
PB
0xC2
5
PBASTAT
R
PB
PB
0xC2
0xC3
[4:0]
[7:5]
-
-
R
R
Reserved.
Reserved.
Global Off Control. Set OFFSYSCLR[ ] to 1 first, then set this bit
to 1 to turn off all outputs.
PB
0xC3
[4]
OFFSYS
R/W
Global Off Control State Clear bit. Set bit to 1, then set OFFSYS
[ ] to 1 to turn off all outputs.
PB
PB
PB
PB
PB
0xC3
0xC3
0xC3
0xC5
0xC5
[3]
[2:1]
0
OFFSYSCLR R/W
-
SIPC
-
R
Reserved.
Software Initiated Power Cycle. When this bit is set, the PMU
commences a power cycle after 8ms delay.
R/W
R
[7:2]
1
Reserved.
Power-cycle Flag. The value of this bit is 1 after a power cycle.
This bit is automatically cleared to 0 after read.
PCSTAT
R/W
Soft-reset Flag. The value of this bit is 1 after a soft-reset. This
bit is automatically cleared to 0 after read.
PB
0xC5
0
SRSTAT
R/W
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