ACT8840
Rev 2, 29-Jan-15
activity for the PMU. In the case where the system
software stops responding and that there is no I2C
transactions for 4s, the watchdog timer expires. As
a result, the PMU either perform a soft-reset or
power cycle, depending on whether WDSREN [ ] or
WDPCEN [ ] is set.
Push-Button Control
The ACT8840 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWRHLD) before nPBIN is de-asserted. If the
microprocessor is unable to complete its power-up
routine successfully before the user releases the
push-button, the ACT8840 automatically shuts the
system down. This provides protection against
accidental or momentary assertions of the push-
button. If desired, longer “push-and-hold” times can
be implemented by simply adding an additional time
delay before asserting PWREN or PWRHLD.
Software-Initiated Power Cycle
ACT8840 supports software-initiated power cycle.
Once the SIPC[ ] bit is set, the PMU waits for 8ms
and then initiate a power cycle to restart the entire
system.
Control Sequences
The ACT8840 features
a
variety of control
sequences that are optimized for supporting system
enable and disable.
Enabling/Disabling Sequence
A typical enable sequence is initiated whenever the
nPBIN is asserted low via 50Kꢀ resistance. The
power control diagram is shown in Figure 3. During
the boot sequence, the microprocessor must assert
PWRHLD, and PWREN, to ensure that the system
remains powered after nPBIN is released. Once the
power-up routine is completed, the system remains
enabled after the push-button is released as long as
either PWRHLD is asserted high. If the processor
does not assert PWRHLD before the user releases
the push-button, the boot-up sequence is
terminated and all regulators are disabled. This
provides protection against "false-enable", when the
push-button is accidentally depressed, and also
ensures that the system remains enabled only if the
processor successfully completes the boot-up
sequence.
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before the processor finally de-asserts PWRHLD.
Watch-Dog Supervision
The ACT8840 features a watchdog supervisory
function. An internal watchdog timer of 4s is
unmasked by setting either WDSREN[
]
or
WDPCEN [ ] bit to one. Once enabled, the
watchdog timer is reset whenever there is I2C
Innovative PowerTM
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