ACT5880
Rev 2, 03-Sep-13
TSC ADC ELECTRICAL CHARACTERISTICS
(VVBAT = VVD = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Operation Voltage Range
VVD
TA = -40°C to +85°C
Maximum Available Resolution CLEN=0
2.9
5.5
V
Reference Voltage (VREF
)
2.5
12
bits
V
XPOS, YPOS, XNEG, YNEG, AUX0, AUX1, AUX2.
VREF
6.024
Full Scale Dynamic Range at
Input (FSDRNOTE1
)
AUX3
Absolute DC Conversion Error
TSC Conversion Time
AUX3, measured with VVBAT=3.9V.
-21
21
mV
μs
CLEN=0(for 12 bits resolution), Switch frequency
2MHz.
225
(Counts of internal clock cycles
of the device)
INLNOTE2
-4
-1
5
1
The standard deviation plus the 1st movement of the
worst. INL and DNL are from DC sweep histogram
analysis; Offset and Gain Error are from least square
linear approximation, from data of input in 10% to 90%
FSDR; Effective Numbers of Bits is the worst
FWHMNOTE3 of reading a DC volume in same range.
Test on channel 0 to channel 6 only, 12 bits
conversion.
DNLNOTE2
LSB
OffsetNOTE2
8
Gain ErrorNOTE2
Effective Numbers of BitsNOTE2
Input Impedance
Input capacitance
Input leakage Current
1.5
bit
Mꢀ
pF
11
32
0.1
1
μA
Touch Detection Trap
Thresholds
Voltage at the XPOS when pen touch trapped.
At force driving voltage drop 5%.
V
Force Current
17
4
mA
Force Switch On-Impedance
Conversion Operation Current
Shutdown Current
ꢀ
210
μA
1
NOTE1: DC Full Scale Dynamic Range at input.
NOTE2: Guaranted by design verfication, characterization and production process control.
NOTE3: Full Width of Half Magnititude.
See The TYPICAL PERFORMANCE CHARACTERISTICS for:
The DC Sweep Histogram DNL
Note: Guaranteed by design verification, characterization and production process control.
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