PLUS
ProASIC
Flash Family FPGAs
High-Performance
Global Network
PAD RING
Top Spine
Global Networks
Global
Pads
Global
Pads
Global Spine
Global Ribs
Bottom Spine
Scope of Spine
(Shaded area
plus local RAMs
and I/Os)
PAD RING
Note: This figure shows routing for only one global path.
Figure 1-7 • High-Performance Global Network
Table 1-1 • Clock Spines
APA075
APA150
APA300
APA450
4
APA600
4
APA750 APA1000
Global Clock Networks (Trees)
Clock Spines/Tree
4
6
4
8
4
8
4
16
4
22
12
14
Total Spines
24
32
32
48
56
64
88
Top or Bottom Spine Height (Tiles)
Tiles in Each Top or Bottom Spine
Total Tiles
16
24
32
32
48
64
80
512
3,072
768
6,144
1,024
8,192
1,024
12,288
1,536
21,504
2,048
32,768
2,560
56,320
v5.2
1-7
ACTEL [ Actel Corporation ]
