PLUS
ProASIC
Flash Family FPGAs
High Speed Very Long-Line Resouces
PAD RING
SRAM
SRAM
PAD RING
Figure 1-6 • High-Speed, Very Long-Line Resources
Clock Resources
Clock Trees
The ProASICPLUS family offers powerful and flexible
control of circuit timing through the use of analog
circuitry. Each chip has two clock conditioning blocks
containing a phase-locked loop (PLL) core, delay lines,
phase shifter (0°, 90°, 180°, 270°), clock multiplier/
dividers, and all the circuitry needed for the selection
and interconnection of inputs to the global network
(thus providing bidirectional access to the PLL). This
permits the PLL block to drive inputs and/or outputs via
the two global lines on each side of the chip (four total
lines). This circuitry is discussed in more detail in the
"ProASICPLUS Clock Management System" section on
page 1-13.
One of the main architectural benefits of ProASICPLUS is
the set of power- and delay-friendly global networks.
ProASICPLUS offers four global trees. Each of these trees
is based on a network of spines and ribs that reach all
the tiles in their regions (Figure 1-7 on page 1-7). This
flexible clock tree architecture allows users to map up to
88 different internal/external clocks in an APA1000
device. Details on the clock spines and various numbers
of the family are given in Table 1-1 on page 1-7.
The flexible use of the ProASICPLUS clock spine allows the
designer to cope with several design requirements. Users
implementing clock-resource intensive applications can
easily route external or gated internal clocks using global
routing spines. Users can also drastically reduce delay
penalties and save buffering resources by mapping
critical high fanout nets to spines. For design hints on
using these features, refer to Actel’s Efficient Use of
ProASIC Clock Trees application note.
1-6
v5.2
ACTEL [ Actel Corporation ]
