Device Architecture
an external crystal frequency of 32.768 kHz, the prescaler output clock will toggle at a rate of
32.768 kHz / 128 = 256 Hz.
The RTC is built from and controlled by a set of registers, denoted "Main Registers" in Figure 2-27
on page 2-34. These registers are accessed via the ACM.
The FPGA fabric portion of the Fusion device must be powered up and active at least once to write
to the various registers within the RTC to initialize them for the user’s application. Users set up the
RTC by configuring it from the Actel SmartGen tool, implementing custom logic or programming a
soft microcontroller.
The 40-bit counter and match registers are each divided into five bytes. Each byte is directly
addressable by the ACM. The address map of registers accessed through the ACM and used by the
RTC is shown in Table 2-16 on page 2-36.
Table 2-15 • RTC Macro Signal Description
Signal Name
RTCMATCH
Number of Bits
Direction
Out
Function
1
1
Match between 40-bit counter and match register
RTCPSMMATCH
Out
RTCMATCH connected to voltage regulator power
supply monitor (VRPSM) (Figure 2-30 on page 2-40)
RTCXTLMODE[1:0]
RTCXTLSEL
2
1
1
Out
Out
In
Drives XTLOSC RTCMODE[1:0] pins
Drives XTLOSC SELMODE pin
RTCCLK
RTC clock input from XTLOSC CLKOUT pin
Table 2-16 • RTC ACM Memory Map
ACM_ADDR[7:0] Decimal Register Name
Description
Use
0x40
0x41
0x42
0x43
0x44
0x48
0x49
0x4A
0x4B
0x4C
0x50
0x51
0x52
0x53
0x54
0x58
64
65
66
67
68
72
73
74
75
76
80
81
82
83
84
88
COUNTER0
COUNTER1
COUNTER2
COUNTER3
COUNTER4
Counter bits 7:0
Used to preload the counter to a
specified start point. Default setting
is all zeroes.
Counter bits 15:8
Counter bits 23:16
Counter bits 31:24
Counter bits 39:32
MATCHREG0 Match register bits 7:0
MATCHREG1 Match register bits 15:8
MATCHREG2 Match register bits 23:16
MATCHREG3 Match register bits 31:24
MATCHREG4 Match register bits 39:32
MATCHBITS0 Individual match bits 7:0
MATCHBITS1 Individual match bits 15:8
MATCHBITS2 Individual match bits 23:16
MATCHBITS3 Individual match bits 31:24
MATCHBITS4 Individual match bits 39:32
The RTC uses a 40-bit register to
compare against the 40-bit counter
value to determine when a match
occurs. This 40-bit match register, like
the counter, is broken into 5 bytes
(MATCHREG0–4).
Each bit of the 40-bit counter is
compared to each bit of the 40-bit
match register via XNOR gates. These
40 match bits are partitioned into 5
bytes.
CTRL_STAT
Control (write)
(read) register bits 7:0
/
Status Control (write) / Status (read) register
bits 7:0
0x59
89
TEST_REG
Test register(s)
Test register(s)
Note: Accessing RTC Registers: When reading the RTC count or match register, which operates in the XTLCLK
domain, the appropriate 40-bit value is first copied to a capture register through clock synchronization
circuitry, if and only if the least significant byte of that set of register is addressed. Higher-order bytes of
the same set of registers captured with the LSB can then be read on immediately later read cycles. Higher-
order bytes of that set of registers can be read in any order but must be read before switching to a
different set of registers to ensure data consistency. For example, RTC counter address ranges from 0x40
to 0x44, register 0x40 must be accessed first before accessing addresses 0x41, 0x42, 0x43, and 0x44 to get
the full 40-bit value.
2-36
Preliminary v1.7
ACTEL [ Actel Corporation ]
