Device Architecture
No-Glitch MUX (NGMUX)
Positioned downstream from the PLL/CCC blocks, the NGMUX provides a special switching
sequence between two asynchronous clock domains that prevents generating any unwanted
narrow clock pulses. The NGMUX is used to switch the source of a global between three different
clock sources. Allowable inputs are either two PLL/CCC outputs or a PLL/CCC output and a regular
net, as shown in Figure 2-24. The GLMUXCFG[1:0] configuration bits determine the source of the
CLK inputs (i.e., internal signal or GLC). These are set by SmartGen during design but can also be
changed by dynamically reconfiguring the PLL. The GLMUXSEL[1:0] bits control which clock source
is passed through the NGMUX to the global network (GL). See Table 2-14.
Crystal Oscillator
RC Oscillator
W I/O Ring
GLMUXCFG[1:0]
CCC/PLL
GLINT
To Clock Rib Driver
GL
PLL/
CCC
GLA
GLC
NGMUX
Clock I/Os
From FPGA Core
PWR UP
GLMUXSEL[1:0]
Figure 2-24 • NGMUX
Table 2-14 • NGMUX Configuration and Selection Table
Selected Input
GLMUXCFG[1:0]
GLMUXSEL[1:0]
Signal
MUX Type
00
X
X
X
X
0
1
0
1
GLA
2-to-1 GLMUX
GLC
01
GLA
2-to-1 GLMUX
GLINT
2-32
Preliminary v1.7
ACTEL [ Actel Corporation ]
