欢迎访问ic37.com |
会员登录 免费注册
发布采购

AFS600-2FGG256I 参数 Datasheet PDF下载

AFS600-2FGG256I图片预览
型号: AFS600-2FGG256I
PDF下载: 下载PDF文件 查看货源
内容描述: Actel的Fusion混合信号FPGA [Actel Fusion Mixed-Signal FPGAs]
分类和应用:
文件页数/大小: 318 页 / 10484 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号AFS600-2FGG256I的Datasheet PDF文件第51页浏览型号AFS600-2FGG256I的Datasheet PDF文件第52页浏览型号AFS600-2FGG256I的Datasheet PDF文件第53页浏览型号AFS600-2FGG256I的Datasheet PDF文件第54页浏览型号AFS600-2FGG256I的Datasheet PDF文件第56页浏览型号AFS600-2FGG256I的Datasheet PDF文件第57页浏览型号AFS600-2FGG256I的Datasheet PDF文件第58页浏览型号AFS600-2FGG256I的Datasheet PDF文件第59页  
Actel Fusion Mixed-Signal FPGAs  
1.5 V Voltage Regulator  
The VR generates a 1.5 V power supply from the 3.3 V power supply. The 1.5 V output is intended  
to supply all 1.5 V needs of the Fusion device. This regulator requires an external bipolar pass  
transistor (Figure 2-29). The VR can drive up to 20 mA of current through the PTBASE pad. The  
amount of 1.5 V current available is dependent upon the gain of the external pass transistor used.  
Enable for this block is generated in the VR Logic block or from the PUB pin.  
The VR is forced "on" with TRST high or floating (internal pull-up), so an external pull-down is  
required on TRST if the customer desires to power-down the VR.  
The 1.5 V is not supplied internally to the Fusion device. It must be routed externally to the VCC pins  
on the device. Therefore the user is not required to use the VR and can use an off-chip 1.5 V supply  
if desired.  
On-Chip Off-Chip  
VCC33A  
RTC FPGA  
VCC33A  
PTBASE  
1.5 V  
Regulator  
PTEM  
1.5 V Out  
PDVR  
VCC33A  
1 µA  
PUB  
Power-Up/Down Control Circuit  
Figure 2-29 • Voltage Regulator  
Preliminary v1.7  
2-39  
 复制成功!