Device Architecture
VersaNet Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are dependent upon I/O standard, and the clock may
be driven and conditioned internally by the CCC module. Table 2-5, Table 2-6, Table 2-7, and
Table 2-8 on page 2-19 present minimum and maximum global clock delays within the
device.Minimum and maximum delays are measured with minimum and maximum loading,
respectively.
Timing Characteristics
Table 2-5 • AFS1500 Global Resource Timing
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
1.53
1.53
1.75
1.79
1.74
1.75
1.99
2.04
2.05
2.05
2.34
2.40
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width HIGH for Global
Clock
tRCKMPWL Minimum Pulse Width LOW for Global
Clock
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.26
0.29
0.34
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
Table 2-6 • AFS600 Global Resource Timing
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
1.27
1.26
1.49
1.54
1.44
1.44
1.70
1.75
1.69
1.69
2.00
2.06
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width HIGH for Global
Clock
tRCKMPWL Minimum Pulse Width LOW for Global
Clock
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.27
0.31
0.36
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
2-18
Preliminary v1.7
ACTEL [ Actel Corporation ]
