Device Architecture
Table 2-32 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
–2
–1
Std. Units
Address Setup time
0.25
0.00
0.09
0.06
0.18
0.00
0.28 0.33
0.00 0.00
0.10 0.12
0.07 0.08
0.21 0.25
0.00 0.00
2.46 2.89
1.02 1.20
TBD TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address Hold time
tENS
REN_B,WEN_B Setup time
REN_B, WEN_B Hold time
Input data (DI) Setup time
Input data (DI) Hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
tWRO
Clock High to New Data Valid on DO (output retained, WMODE = 0) 2.16
Clock High to New Data Valid on DO (pipelined) 0.90
Address collision clk-to-clk delay for reliable read access after write TBD
on same address
tCCKH
Address collision clk-to-clk delay for reliable write access after TBD
write/read on same address
TBD TBD
ns
tRSTBQ
RESET_B Low to Data Out Low on DO (flow-through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
0.92
0.92
0.29
1.50
0.21
3.23
310
1.05 1.23
1.05 1.23
0.33 0.38
1.71 2.01
0.24 0.29
3.68 4.32
ns
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle time
FMAX
Maximum Clock Frequency
272
231 MHz
Note: For the derating values at specific junction temperature and voltage-supply levels, refer to Table 3-7 on
page 3-9.
2-72
Preliminary v1.7
ACTEL [ Actel Corporation ]
