Actel Fusion Mixed-Signal FPGAs
Timing Characteristics
Table 2-31 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
–2
–1
Std. Units
Address Setup time
0.25
0.00
0.14
0.10
0.23
0.02
0.18
0.00
1.79
2.36
0.89
0.28 0.33
0.00 0.00
0.16 0.19
0.11 0.13
0.27 0.31
0.02 0.02
0.21 0.25
0.00 0.00
2.03 2.39
2.68 3.15
1.02 1.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address Hold time
tENS
REN_B,WEN_B Setup time
tENH
tBKS
tBKH
tDS
REN_B, WEN_B Hold time
BLK_B Setup time
BLK_B Hold time
Input data (DI) Setup time
tDH
Input data (DI) Hold time
tCKQ1
Clock High to New Data Valid on DO (output retained, WMODE = 0)
Clock High to New Data Valid on DO (flow-through, WMODE = 1)
Clock High to New Data Valid on DO (pipelined)
tCKQ2
tWRO
Address collision clk-to-clk delay for reliable read access after write TBD
on same address
TBD
TBD
tCCKH
Address collision clk-to-clk delay for reliable write access after TBD
write/read on same address
TBD
TBD
ns
tRSTBQ
RESET_B Low to Data Out Low on DO (flow-through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
0.92
0.92
0.29
1.50
0.21
3.23
310
1.05 1.23
1.05 1.23
0.33 0.38
1.71 2.01
0.24 0.29
3.68 4.32
ns
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle time
FMAX
Maximum Clock Frequency
272
231 MHz
Note: For the derating values at specific junction temperature and voltage-supply levels, refer to Table 3-7 on
page 3-9.
Preliminary v1.7
2-71