Device Architecture
Flash Memory Block Pin Names
Table 2-19 • Flash Memory Block Pin Names
Interface Name
ADDR[17:0]
Width Direction
Description
18
1
In
In
Byte offset into the FB. Byte-based address.
AUXBLOCK
When asserted, the page addressed is used to access the auxiliary block
within that page.
BUSY
CLK
1
1
Out
In
When asserted, indicates that the FB is performing an operation.
User interface clock. All operations and status are synchronous to the
rising edge of this clock.
DATAWIDTH[1:0]
2
In
Data width
00 = 1 byte in RD/WD[7:0]
01 = 2 bytes in RD/WD[15:0]
1x = 4 bytes in RD/WD[31:0]
DISCARDPAGE
ERASEPAGE
1
1
1
1
1
In
In
In
In
In
When asserted, the contents of the Page Buffer are discarded so that a
new page write can be started.
When asserted, the contents of the Page Buffer are discarded so that a
new page write can be started.
LOCKREQUEST
OVERWRITEPAGE
When asserted, indicates to the JTAG controller that the FPGA
interface is accessing the FB.
When asserted, the page addressed is overwritten with the contents of
the Page Buffer if the page is writable.
OVERWRITEPROTE
CT
When asserted, all program operations will set the overwrite protect
bit of the page being programmed.
PAGESTATUS
1
1
In
In
When asserted with REN, initiates a read page status operation.
PAGELOSSPROTECT
When asserted, a modified Page Buffer must be programmed or
discarded before accessing a new page.
PIPE
1
1
In
In
Adds a pipeline stage to the output for operation above 50 MHz.
PROGRAM
When asserted, writes the contents of the Page Buffer into the FB page
addressed.
RD[31:0]
32
Out
Read data; data will be valid from the first non-busy cycle (BUSY = 0)
after REN has been asserted.
READNEXT
REN
1
1
1
1
In
In
In
In
When asserted with REN, initiates a read-next operation.
When asserted, initiates a read operation.
RESET
When asserted, resets the state of the FB (active low).
SPAREPAGE
When asserted, the sector addressed is used to access the spare page
within that sector.
2-42
Preliminary v1.7
ACTEL [ Actel Corporation ]
