Device Architecture
Voltage Regulator Power Supply Monitor (VRPSM)
As the functions of the VR Logic and Power System Monitor work closely together to control the
power-up state of the FPGA core, these functions were combined into a single VRPSM macro
(Figure 2-30).
The signals for the VRPSM macro are listed in Table 2-18. The PUB input comes from the PUB pin on
the device and can be pulled LOW by a signal external to the Fusion device. This can be used to
wake up the device. The inputs VRINITSTATE and RTCPSMMTACH come from the VR Init and RTC
blocks, respectively, and either can initiate a VR power-up. The detailed description is available in
the Fusion Handbook.
PUB
FPGAGOOD
PUCORE
VRPU
VRINITSTATE
RTCPSMMATCH
Figure 2-30 • VRPSM Macro
Table 2-18 • Signals for VRPSM Macro
Number of
Signal Name
Bits
Direction
Function
PUB
1
Input
Active low signal to power up the FPGA core via
the 1.5 V regulator.
In this reference design, PUB is on the top level,
connected to an external switch.
VRPU
1
1
Input
Input
When this pin is at logic 1, the FPGA core will be
turned off via the voltage regulator.
VRINITSTATE
This feature is not used in this reference design and
is not shown in the macro generated by SmartGen.
If used, the signal enables you to set your voltage
regulator output at power-up (ON or OFF).
RTCPSMMATCH
1
Input
This feature is not used in this reference design. If
used, this active high signal is driven by the RTC’s
match signal to indicate that the RTC counter value
matches the pre-defined Match register value set in
SmartGen.
FPGAGOOD
PUCORE
1
1
Output
Output
Logic 1 indicates that FPGA is logically functional.
Logic 1 indicates that FPGA is logically functional.
2-40
Preliminary v1.7
ACTEL [ Actel Corporation ]
