Pin Description
CLK
Clock (Input)
MODE
Mode (Input)
ACT 1 only. TTL Clock input for global clock distribution
network. The Clock input is buffered prior to clocking the
logic modules. This pin can also be used as an I/O.
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/Os. To provide debugging capability, the MODE
pin should be terminated to GND through a 10 kΩ resistor so
that the MODE pin can be pulled high when required.
CLKA
Clock A (Input)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for
global clock distribution networks. The Clock input is
buffered prior to clocking the logic modules. This pin can also
be used as an I/O.
NC
No Connection
This pin is not connected to circuitry within the device.
CLKB
Clock B (Input)
PRA, I/O
Probe A (Output)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for
global clock distribution networks. The Clock input is
buffered prior to clocking the logic modules. This pin can also
be used as an I/O.
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
DCLK
Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
LOW supply voltage.
PRB, I/O
Probe B (Output)
HCLK
Dedicated (Hard-wired) Array
Clock (Input)
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
ACT 3 only. TTL Clock input for sequential modules. This
input is directly wired to each S-module and offers clock
speeds independent of the number of S-modules being driven.
This pin can also be used as an I/O.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, tristate, or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. In the ACT 3 and
3200DX families, unused I/Os are automatically tri-stated.
With this configuration, the input buffer internal to the I/O
module is disabled. In the ACT 1, ACT 2 and 1200XL families,
unused I/Os are automatically configured as bi-directional
buffers where each buffer is configured as a LOW driver.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
VCC
5.0V Supply Voltage
IOCLK
Dedicated (Hard-wired) I/O
Clock (Input)
HIGH supply voltage.
QCLKA/B,C,D Quadrant Clock (Input/Output)
3200DX only. These four pins are the quadrant clock inputs.
When not used as a register control signal, these pins can
function as general purpose I/O.
ACT 3 only. TTL Clock input for I/O modules. This input is
directly wired to each I/O module and offers clock speeds
independent of the number of I/O modules being driven. This
pin can also be used as an I/O.
TCK
Test Clock
IOPCL
Dedicated (Hard-wired) I/O
Preset/Clear (Input)
Clock signal to shift the JTAG data into the device. This pin
functions as an I/O when the JTAG fuse is not programmed.
JTAG pins are only available in the 3200DX device.
ACT 3 only. TTL input for I/O preset or clear. This global input
is directly wired to the preset and clear inputs of all I/O
registers. This pin functions as an I/O when no I/O preset or
clear macros are used.
56
ACTEL [ Actel Corporation ]
