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A1240DX-1PLB 参数 Datasheet PDF下载

A1240DX-1PLB图片预览
型号: A1240DX-1PLB
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A1240DX-1PLB的Datasheet PDF文件第46页浏览型号A1240DX-1PLB的Datasheet PDF文件第47页浏览型号A1240DX-1PLB的Datasheet PDF文件第48页浏览型号A1240DX-1PLB的Datasheet PDF文件第49页浏览型号A1240DX-1PLB的Datasheet PDF文件第51页浏览型号A1240DX-1PLB的Datasheet PDF文件第52页浏览型号A1240DX-1PLB的Datasheet PDF文件第53页浏览型号A1240DX-1PLB的Datasheet PDF文件第54页  
Integrator Series FPGAs: 1200XL and 3200DX Families  
A32200DX Timing Characteristics (continued)  
(Worst-Case Commercial Conditions V  
= 4.75 V, T = 70°C)  
J
CC  
3.3V ‘Std’  
Speed  
‘–3’ Speed  
‘–2’ Speed  
‘–1’ Speed  
‘Std’ Speed  
‘–F’ Speed  
Parameter  
Description  
Min. Max. Min.  
Max. Min. Max. Min. Max. Min. Max. Min. Max. Units  
1
TTL Output Module Timing  
t
t
t
t
t
t
t
t
t
t
t
t
Data-to-Pad High  
3.7  
4.5  
4.8  
5.2  
8.3  
8.3  
8.3  
8.9  
4.3  
5.3  
5.6  
6.0  
9.7  
9.7  
9.7  
10.5  
4.9  
6.0  
5.8  
7.1  
8.3  
6.8  
8.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DLH  
DHL  
ENZH  
ENZL  
ENHZ  
ENLZ  
GLH  
GHL  
LSU  
Data-to-Pad Low  
10.1  
10.7  
11.5  
18.5  
18.5  
18.5  
20.0  
Enable-Pad Z to High  
6.4  
7.5  
8.8  
Enable-Pad Z to Low  
6.9  
8.1  
9.5  
Enable-Pad High to Z  
11.1  
11.1  
11.1  
11.9  
13.0  
13.0  
13.0  
14.0  
15.2  
15.2  
15.2  
16.5  
Enable-Pad Low to Z  
G-to-Pad High  
G-to-Pad Low  
I/O Latch Output Set-Up  
I/O Latch Output Hold  
0.26  
0.0  
0.3  
0.0  
0.3  
0.0  
0.4  
0.0  
0.6  
0.0  
0.5  
0.0  
LH  
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O  
Array Latch Clock-Out (Pad-to-Pad) 32 I/O  
Capacitive Loading, Low to High  
Capacitive Loading, High to Low  
8.4  
9.8  
11.1  
15.7  
0.04  
0.06  
0.05  
13.1  
18.5  
0.05  
0.07  
0.06  
18.7  
26.5  
0.07  
0.10  
0.09  
15.4  
21.7  
LCO  
ACO  
11.8  
0.03  
0.04  
0.04  
13.9  
d
d
0.035  
0.05  
0.06 ns/pF  
0.08 ns/pF  
TLH  
THL  
t
Hard-Wired Wide-Decode Output  
1
0.045  
0.07  
ns  
WDO  
CMOS Output Module Timing  
t
t
t
t
t
t
t
t
t
t
t
Data-to-Pad High  
Data-to-Pad Low  
Enable-Pad Z to High  
Enable-Pad Z to Low  
Enable-Pad High to Z  
Enable-Pad Low to Z  
G-to-Pad High  
4.5  
3.7  
4.8  
5.2  
8.3  
8.3  
8.3  
8.9  
5.3  
4.3  
5.6  
6.0  
9.7  
9.7  
9.7  
10.5  
6.0  
4.9  
5.8  
7.1  
8.3  
6.8  
8.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DLH  
DHL  
ENZH  
ENZL  
ENHZ  
ENLZ  
GLH  
GHL  
LSU  
10.1  
10.7  
11.5  
18.5  
18.5  
18.5  
20.0  
6.4  
7.5  
8.8  
6.9  
8.1  
9.5  
11.1  
11.1  
11.1  
11.9  
13.0  
13.0  
13.0  
14.0  
15.2  
15.2  
15.2  
16.5  
G-to-Pad Low  
I/O Latch Set-Up  
I/O Latch Hold  
0.26  
0.0  
0.3  
0.0  
0.3  
0.0  
0.4  
0.0  
0.6  
0.0  
0.5  
0.0  
LH  
I/O Latch Clock-Out (Pad-to-Pad)  
32 I/O  
LCO  
9.9  
11.6  
13.2  
15.5  
22.3  
18.2  
25.6  
ns  
ns  
t
ACO  
Array Latch Clock-Out (Pad-to-Pad) 32 I/O  
13.9  
0.04  
0.04  
0.04  
16.3  
0.05  
18.5  
0.06  
0.05  
0.05  
21.8  
0.07  
0.06  
0.06  
31.2  
0.10  
0.09  
0.09  
d
d
Capacitive Loading, Low to High  
Capacitive Loading, High to Low  
Hard-Wired Wide-Decode Output  
0.08 ns/pF  
0.07 ns/pF  
TLH  
THL  
0.045  
0.045  
t
0.07  
ns  
WDO  
Note:  
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual performance.  
50  
Discontinued – v3.0  
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