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A1240DX-1PLB 参数 Datasheet PDF下载

A1240DX-1PLB图片预览
型号: A1240DX-1PLB
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A1240DX-1PLB的Datasheet PDF文件第45页浏览型号A1240DX-1PLB的Datasheet PDF文件第46页浏览型号A1240DX-1PLB的Datasheet PDF文件第47页浏览型号A1240DX-1PLB的Datasheet PDF文件第48页浏览型号A1240DX-1PLB的Datasheet PDF文件第50页浏览型号A1240DX-1PLB的Datasheet PDF文件第51页浏览型号A1240DX-1PLB的Datasheet PDF文件第52页浏览型号A1240DX-1PLB的Datasheet PDF文件第53页  
Integrator Series FPGAs: 1200XL and 3200DX Families  
A32200DX Timing Characteristics (continued)  
(Worst-Case Commercial Conditions V  
= 4.75 V, T = 70°C)  
J
CC  
3.3V ‘Std’  
Speed  
‘–3’ Speed  
‘–2’ Speed  
‘–1’ Speed  
‘Std’ Speed  
‘–F’ Speed  
Parameter  
Description  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units  
Input Module Propagation Delays  
t
t
Input Data Pad-to-Y  
1.4  
3.3  
1.65  
3.2  
1.9  
4.3  
2.2  
5.1  
2.9  
7.3  
2.5  
6.0  
ns  
INPY  
1
INGO  
Input Latch Gate-to-Output  
ns  
ns  
ns  
ns  
1
t
t
t
Input Latch Hold  
0.0  
0.45  
4.4  
0.0  
0.52  
5.2  
0.0  
0.6  
5.9  
0.0  
0.7  
6.9  
0.0  
1.0  
9.8  
0.0  
0.8  
8.1  
INH  
INSU  
ILA  
1
Input Latch Set-Up  
1
Latch Active Pulse Width  
Input Module Predicted Routing Delays  
t
t
t
t
t
t
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
Decode-to-Output Delay  
1.9  
2.5  
3.3  
3.9  
5.0  
0.3  
2.2  
2.9  
3.9  
4.5  
6.0  
0.37  
2.6  
3.3  
4.4  
5.2  
6.7  
0.4  
3.0  
3.9  
5.2  
6.1  
7.9  
0.5  
4.2  
5.5  
7.6  
8.7  
11.2  
0.7  
3.5  
4.5  
6.1  
7.1  
9.3  
0.6  
ns  
ns  
ns  
ns  
ns  
ns  
IRD1  
IRD2  
IRD3  
IRD4  
IRD5  
IRDD  
Global Clock Network  
t
t
t
t
t
t
t
t
f
Input Low to High  
FO=32  
FO=635  
5.3  
6.1  
6.2  
7.2  
7.1  
8.2  
8.3  
9.6  
11.8  
13.7  
9.7  
11.3  
ns  
ns  
CKH  
Input High to Low  
FO=32  
FO=635  
5.2  
6.8  
6.2  
8.0  
7.0  
9.0  
8.2  
10.6  
11.7  
15.1  
9.6  
12.8  
ns  
ns  
CKL  
FO=32  
FO=635  
2.7  
2.9  
3.2  
3.45  
3.7  
3.9  
4.3  
4.6  
6.1  
6.6  
5.0  
5.4  
ns  
ns  
PWH  
PWL  
CKSW  
SUEXT  
HEXT  
P
Minimum Pulse Width High  
FO=32  
FO=635  
2.7  
2.9  
3.2  
3.45  
3.7  
3.9  
4.3  
4.6  
6.1  
6.6  
5.0  
5.4  
ns  
ns  
Minimum Pulse Width Low  
Maximum Skew  
FO=32  
FO=635  
0.6  
0.6  
0.75  
0.75  
0.9  
0.9  
1.0  
1.0  
1.4  
1.4  
1.1  
1.1  
ns  
ns  
FO=32  
FO=635  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
ns  
ns  
Input Latch External Set-Up  
Input Latch External  
Hold  
FO=32  
FO=635  
2.2  
2.7  
2.6  
3.2  
2.9  
3.7  
3.4  
4.3  
4.9  
6.1  
4.0  
5.0  
ns  
ns  
Minimum Period  
(1/fmax)  
FO=32  
FO=635  
5.5  
6.1  
6.5  
7.2  
7.4  
8.2  
8.7  
9.6  
12.4  
13.7  
10.2  
11.2  
ns  
ns  
Maximum Datapath  
Frequency  
FO=32  
FO=635  
165  
151  
153.  
140  
132  
121  
115  
105  
80  
73  
98  
90  
MHz  
MHz  
HMAX  
Note:  
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual performance.  
Discontinued – v3.0  
49  
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