欢迎访问ic37.com |
会员登录 免费注册
发布采购

A1240A-1PL176C 参数 Datasheet PDF下载

A1240A-1PL176C图片预览
型号: A1240A-1PL176C
PDF下载: 下载PDF文件 查看货源
内容描述: ACT2系列FPGA [ACT2 Family FPGAs]
分类和应用:
文件页数/大小: 38 页 / 610 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A1240A-1PL176C的Datasheet PDF文件第1页浏览型号A1240A-1PL176C的Datasheet PDF文件第3页浏览型号A1240A-1PL176C的Datasheet PDF文件第4页浏览型号A1240A-1PL176C的Datasheet PDF文件第5页浏览型号A1240A-1PL176C的Datasheet PDF文件第6页浏览型号A1240A-1PL176C的Datasheet PDF文件第7页浏览型号A1240A-1PL176C的Datasheet PDF文件第8页浏览型号A1240A-1PL176C的Datasheet PDF文件第9页  
ACT2 Family FPGAs  
Description  
The ACT2 family represents Actels second generation of  
field programmable gate arrays (FPGAs). The ACT 2 family  
presents a two-module architecture, consisting of C-modules  
and S-modules. These modules are optimized for both  
combinatorial and sequential designs. Based on Actels  
patented channeled array architecture, the ACT 2 family  
provides significant enhancements to gate density and  
performance while maintaining downward compatibility  
technology. This revolutionary architecture offers gate array  
design flexibility, high performance, and fast  
time-to-production with user programming. The ACT 2  
family is supported by the Designer and Designer Advantage  
Systems, which offers automatic pin assignment, validation  
of electrical and design rules, automatic placement and  
routing, timing analysis, user programming, and diagnostic  
probe capabilities. The systems are supported on the  
following platforms: 386/486PC, Sun, and HP™  
workstations. The systems provide CAE interfaces to the  
following design environments: Cadence, Viewlogic®,  
Mentor Graphics®, and OrCAD.  
with the ACT  
1 design environment and upward  
compatibility with the ACT 3 design environment. The  
devices are implemented in silicon gate, 1.0-µm, two-level  
metal CMOS, and employ Actels PLICE® antifuse  
Ordering Information  
A1280  
A
1
PG  
176  
C
Application (Temperature Range)  
C = Commercial (0 to +70°C)  
I
= Industrial (–40 to +85°C)  
M = Military (–55 to +125°C)  
B = MIL-STD-883  
Package Lead Count  
Package Type  
PL = Plastic J-Leaded Chip Carrier  
PQ = Plastic Quad Flat Pack  
CQ = Ceramic Quad Flat Pack  
PG = Ceramic Pin Grid Array  
TQ = Thin (1.4 mm) Quad Flat Pack  
VQ = Very Thin (1.0 mm) Quad Flat Pack  
Speed Grade  
Blank = Standard Speed  
–1 = Approximately 15% faster than Standard  
–2 = Approximately 25% faster than Standard  
Die Revision  
A = 1.0-µm CMOS process  
Part Number  
A1225 = 2500 Gates  
A1240 = 4000 Gates  
A1280 = 8000 Gates  
2
v4.0  
 复制成功!