ACT™ 2 Family FPGAs
ACT 2 Timing Model*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
Combinatorial
Logic Module
I/O Module
t
INYL = 2.6 ns
tIRD2 = 4.8 ns†
tDLH = 8.0 ns
tRD1 = 1.4 ns
tRD2 = 1.7 ns
D
Q
tPD = 3.8 ns
tRD4 = 3.1 ns
tRD8 = 4.7 ns
I/O Module
G
t
DLH = 8.0 ns
Sequential
Logic Module
tINH = 2.0 ns
tINSU = 4.0 ns
tINGL = 4.7 ns
Combin-
atorial
Logic
D
D
G
Q
Q
tRD1 = 1.4 ns
tENHZ = 7.1 ns
included
in t
SUD
tOUTH = 0.0 ns
tOUTSU = 0.4 ns
tGLH = 9.0 ns
tCO = 3.8 ns
tSUD = 0.4 ns
tHD = 0.0 ns
ARRAY
CLOCKS
tCKH = 11.8 ns
FO = 256
FMAX = 100 MHz
*Values shown for A1240A-2 at worst-case commercial conditions.
† Input Module Predicted Routing Delay
v4.0
7
ACTEL [ Actel Corporation ]
