ACT™ 2 Family FPGAs
Parameter Measurement
Output Buffer Delays
E
D
PAD To AC test loads (shown below)
TRIBUFF
VCC
VCC
VCC
In
GND
1.5 V
50%
VOH
E
GND
10%
50%
E
GND
90%
50%
50%
VCC
50%
VOH
50%
1.5 V
VOL
PAD
VOL
PAD
PAD
GND
1.5 V
1.5 V
tDLH
tDHL
tENZL
tENLZ
tENZH
tENHZ
AC Test Loads
Load 1
Load 2
(Used to measure propagation delay)
(Used to measure rising/falling edges)
VCC
GND
To the output under test
50 pF
R to VCC for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 kΩ
To the output under test
50 pF
Input Buffer Delays
Module Delays
S
A
B
Y
Y
PAD
INBUF
VCC
GND
S, A or B
50% 50%
VCC
3 V
50%
Y
50%
PAD
0 V
50%
1.5 V
VCC
1.5 V
GND
tPLH
tPHL
Y
GND
50%
VCC
50%
Y
GND
tPLH
50%
tPHL
tINYH
tINYL
8
v4.0
ACTEL [ Actel Corporation ]
