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A1225DX-1PLC 参数 Datasheet PDF下载

A1225DX-1PLC图片预览
型号: A1225DX-1PLC
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
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Integrator Series FPGAs: 1200XL and 3200DX Families  
A1280XL Timing Characteristics (continued)  
(Worst-Case Commercial Conditions V  
= 4.75 V, T = 70°C)  
CC  
‘–2’ Speed  
Min. Max.  
J
3.3V ‘Std’  
Speed  
‘–1’ Speed  
Min. Max.  
‘Std’ Speed  
‘–F’ Speed  
Min. Max.  
Parameter  
Description  
1
Min.  
Max.  
Min.  
Max.  
Units  
TTL Output Module Timing  
t
t
t
t
t
t
t
t
t
Data-to-Pad High  
Data-to-Pad Low  
Enable-Pad Z to High  
Enable-Pad Z to Low  
Enable-Pad High to Z  
Enable-Pad Low to Z  
G-to-Pad High  
3.8  
4.1  
3.8  
4.1  
5.4  
5.4  
4.2  
4.7  
4.3  
4.6  
4.3  
4.7  
6.1  
6.1  
4.8  
5.4  
5.0  
5.4  
5.0  
5.5  
7.2  
7.2  
5.6  
6.3  
7.1  
7.7  
6.0  
6.5  
6.0  
6.6  
8.6  
8.6  
6.7  
7.6  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DLH  
DHL  
7.1  
ENZH  
ENZL  
ENHZ  
ENLZ  
GLH  
7.7  
10.3  
10.3  
8.0  
G-to-Pad Low  
9.0  
GHL  
I/O Latch Clock-Out (Pad-to-Pad),  
64 Clock Loading  
LCO  
9.8  
11.0  
13.1  
18.7  
15.7  
ns  
t
Array Clock-Out (Pad-to-Pad),  
64 Clock Loading  
ACO  
13.9  
0.04  
0.05  
15.7  
0.04  
0.06  
18.5  
0.05  
0.07  
26.4  
0.06  
0.08  
22.2  
0.06  
0.08  
ns  
d
d
Capacitive Loading, Low to High  
ns/pF  
ns/pF  
TLH  
THL  
Capacitive Loading, High to Low  
1
CMOS Output Module Timing  
t
t
t
t
t
t
t
t
t
Data-to-Pad High  
Data-to-Pad Low  
Enable-Pad Z to High  
Enable-Pad Z to Low  
Enable-Pad High to Z  
Enable-Pad Low to Z  
G-to-Pad High  
4.8  
3.4  
3.8  
4.1  
5.4  
5.4  
4.2  
4.7  
5.4  
3.8  
4.3  
4.7  
6.1  
6.1  
4.8  
5.4  
6.4  
4.5  
5.0  
5.5  
7.2  
7.2  
5.6  
6.3  
9.1  
6.4  
7.7  
5.4  
6.0  
6.6  
8.6  
8.6  
6.7  
7.6  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DLH  
DHL  
7.1  
ENZH  
ENZL  
ENHZ  
ENLZ  
GLH  
7.9  
10.3  
10.3  
8.0  
G-to-Pad Low  
9.0  
GHL  
I/O Latch Clock-Out (Pad-to-Pad),  
64 Clock Loading  
LCO  
11.6  
13.0  
15.5  
22.2  
18.6  
ns  
t
Array Clock-Out (Pad-to-Pad),  
64 Clock Loading  
ACO  
16.4  
0.05  
0.05  
18.5  
0.06  
0.05  
21.8  
0.07  
0.06  
31.2  
0.08  
0.07  
26.2  
0.08  
0.07  
ns  
d
d
Capacitive Loading, Low to High  
Capacitive Loading, High to Low  
ns/pF  
ns/pF  
TLH  
THL  
Note:  
1. Delays based on 35 pF loading.  
Discontinued – v3.0  
39  
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