Integrator Series FPGAs: 1200XL and 3200DX Families
A32100DX Timing Characteristics
(Worst-Case Commercial Conditions V
= 4.75 V, T = 70°C)
J
CC
3.3V ‘Std’
Speed
‘–3 Speed
‘–2 Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic ModulePropagation Delays
Combinatorial Functions
t
t
Internal Array Module Delay
Internal Decode Module Delay
2.2
2.4
2.6
2.7
3.0
3.1
3.5
3.7
5.2
5.7
4.1
4.3
ns
ns
PD
PDD
Predicted Module Routing Delays
tRD1
tRD2
tRD3
tRD4
tRD5
tRDD
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
1.0
1.4
1.8
2.4
4.2
0.3
1.1
1.7
1.3
1.9
2.5
3.1
5.6
0.4
1.5
2.2
2.9
3.7
6.6
0.5
3.3
4.3
1.7
2.5
3.4
4.3
7.7
0.6
ns
ns
ns
ns
ns
ns
2.1
5.2
2.7
6.5
5.0
10.0
0.4
0.37
Sequential Timing Characteristics
tCO
Flip-Flop Clock-to-Output
2.2
2.2
2.6
2.6
3.0
3.0
3.5
3.5
5.0
5.0
4.1
4.1
ns
ns
ns
ns
ns
ns
ns
ns
tGO
Latch Gate-to-Output
tSU
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset to Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
0.3
0.0
0.37
0.0
0.4
0.0
0.5
0.0
0.7
0.0
0.6
0.0
tH
tRO
2.2
2.6
3.0
3.5
5.0
4.1
tSUENA
tHENA
tWCLKA
tWASYN
0.6
0.0
3.1
0.75
0.0
0.9
0.0
4.2
1.0
0.0
4.9
1.4
0.0
7.0
0.85
0.0
3.7
5.7
Flip-Flop (Latch) Asynchronous Pulse
Width
4.1
4.8
5.4
6.4
7.0
7.5
ns
40
Discontinued – v3.0
ACTEL [ Actel Corporation ]
