Integrator Series FPGAs: 1200XL and 3200DX Families
A3265DX Timing Characteristics (continued)
(Worst-Case Commercial Conditions V
= 4.75 V, T = 70°C)
J
CC
‘–2’ Speed
Min. Max.
3.3V ‘Std’
Speed
‘–1’ Speed
Min. Max.
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
t
t
t
t
t
Input Data Pad-to-Y
Input Latch Gate-to-Output
Input Latch Hold
1.4
3.3
1.6
3.7
1.9
4.4
2.4
5.7
2.1
4.8
ns
ns
ns
ns
ns
INPY
INGO
INH
0.0
0.5
5.1
0.0
0.6
5.9
0.0
0.7
6.9
0.0
0.9
9.0
0.0
0.8
7.7
Input Latch Set-Up
INSU
ILA
Latch Active Pulse Width
1
Input Module Predicted Routing Delays
t
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
3.2
3.6
3.7
4.2
4.5
5.2
7.5
0.4
4.3
4.9
5.3
6.1
8.8
0.5
5.6
6.4
6.9
7.9
11.4
0.7
4.8
5.4
5.9
6.7
9.7
0.6
ns
ns
ns
ns
ns
ns
IRD1
IRD2
IRD3
IRD4
IRD5
IRDD
3.9
4.5
6.6
0.37
Global Clock Network
t
t
t
t
t
t
t
f
Input Low to High
Input High to Low
Minimum Pulse Width
Maximum Skew
FO=32
FO=256
6.3
7.4
7.1
8.4
8.4
9.9
10.9
12.8
9.2
10.9
ns
ns
CKH
FO=32
FO=256
5.9
6.4
6.6
7.3
7.8
8.6
10.1
11.2
8.6
9.5
ns
ns
CKL
FO=32
FO=256
3.2
3.4
3.7
3.9
4.3
4.6
5.6
6.0
4.8
5.1
ns
ns
PW
FO=32
FO=256
0.75
0.75
0.9
0.9
1.0
1.0
1.3
1.3
1.1
1.1
ns
ns
CKSW
SUEXT
HEXT
P
FO=32
FO=256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External Set-Up
FO=32
FO=256
2.5
2.5
2.9
2.9
3.4
3.4
4.4
4.4
3.8
3.8
ns
ns
Input Latch External Hold
Minimum Period (1/fmax)
FO=32
FO=256
5.0
6.0
7.2
8.3
8.3
9.5
11.9
13.6
9.2
10.6
ns
ns
FO=32
FO=256
173
151
138
121
120
105
84
74
108
95
MHz
MHz
MAX
Maximum Datapath Frequency
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
Discontinued – v3.0
35
ACTEL [ Actel Corporation ]
