MIL-PRF-38535K
6.4.40 Class level vs Class. This specification defines the requirements for two class levels of product, class level S and
class level B. Each class level is made up of multiple classes of product, class level S contains the requirements for classes V
and Y product, and class level B contains the requirements for class Q product.
6.4.41 Second party facility. A second party facility is a QA approved facility that acts as a subcontractor to a QML device
manufacturer (e.g. QML Company X using QML Company Y for wafer fabrication, or as a test lab performing TCI testing).
6.4.42 Third party facility. A third party facility is a manufacturer whose facility does not have QML certification. The
process or line used by the QML manufacturer has been certified through the manufacturer for those products supplied as
QML by the manufacturer (e.g., QML Company X using non-QML Company Z to Fab die, only the line or process of the non-
QML company is evaluated for use by the QML manufacturer not the entire facility).
6.4.43 New technology. New technology is defined as a product family, material, or process that has never been previously
characterized and qualified by the manufacturer for a military or space level application.
6.4.44 Mature technology. A mature technology is defined as one which the manufacturer has previously released to
production and has a continuous reliability monitor plan in place to identify major reliability life-limiting mechanisms, detect
long-term product shifts, and generate process data or established proof of stable process and/or equipment with negligible
wear out.
6.4.45 Lot date code. Lot date code will be assigned to identify the devices with the assembly processing and assembly
location. Devices will be traceable through the lot date code to the assembly year, sealing week and assembly location.
6.4.46 Storage temperature. The optimal storage temperature range is defined as -65°C to +150°C.
6.4.47 Multi-product wafer (MPW) . A wafer composed of more than one integrated circuit (microcircuit) design fabricated
on the same wafer. The Multi-product wafer (MPW) may contain a Standard Evaluation Circuit (SEC) design along with
product designs or contain just product designs. MPW wafers will be fabricated as a wafer lot as defined in section 6.4.7.
6.4.48 Package integrity demonstration test plan (PIDTP) . The package integrity demonstration test plan defines to
address the manufacturability, test, quality and reliability issues associated with unique to specific non-traditional
assembly/package techniques.
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ACTEL [ Actel Corporation ]
