TABLE I. Electrical performance characteristics – Continued.
Operation with VCCI = 3.3V (for 3.3V PCI I/O Operations, 8/)
1/ 2/
Conditions 3/
2.25 V ≤ V ≤ 2.75 V
Test
Symbol
Group A
Device
type
Limits
Unit
CCA
subgroups
3.0 V ≤ V
≤ 3.6 V
CCI
-55°C ≤ T ≤ +125°C
C
unless otherwise specified
Min
0.5
Max
High level input voltage
Low level input voltage
Input pull-up voltage
Input leakage current
1,2,3
1,2,3
1,2,3
All
All
All
V
V
V
V
V
CCI
+0.5
IH
V
CCI
-0.5
0.3
V
IL
V
CCI
0.7
I
11/
IPU
I
V
CCI
1,2,3
1,2,3
All
All
-20
20
µA
/ I
0 ≤ V ≤ V
CCI
IH IL
IN
High level output
voltage
0.9
V
V
OH
I
= -500 µA
OUT
V
CCI
Low level output
voltage
1,2,3
All
0.1
V
V
OL
I
= 1500 µA
OUT
V
CCI
Input pin capacitance
Clock pin capacitance
4
4
All
All
10
pF
pF
C
10/
10/
IN
5
12
C
CLK
1/ AC/Timing parameters (subgroup 9, 10, 11) are not directly tested but fully characterized (see note 2/), which are published
on device manufacturer’s data sheet and implemented in manufacturer’s software (see 6.7 and Table IIA note 8/ herein).
2/ Characterization data is taken at initial device introduction and repeated after any design or process changes that may affect
the related parameters. Devices are first 100 percent functionally tested, then benchmark design/timing patterns are
programmed into the devices and then characterized to determine the compliance of the parameters.
3/ All tests shall be performed under the worst-case condition unless otherwise specified.
4/ Standby I
is the total standby current of I
and I
.
CC
CCA
CCI
5/ Devices are functionally tested using a serial scan test method. Data is shifted into the TDI pin and the TCK pin is used as
a clock. The data is used to drive the inputs of the internal logic and I/O modules, allowing a complete functional test to be
performed. The outputs of the module can be read by shifting out the output response or by monitoring the PRA, PRB, or
TDO pins.
6/ Binning circuit delay is defined as the input-to-output delay of a special path called the “binning circuit”. The binning circuit
consists of one input buffer plus a fixed number of combinatorial logic modules plus on output buffer. These modules are
configured as non-inverting buffers and are connected through programmed antifuses with typical capacitive loading.
7/ Binning circuit parameters are tested with typical conditions as listed in this table at room temperature only. Measurement
of binning circuit propagation delay may be used to distinguish standard and –1 speed devices. However, the performance
of user designs are mainly affected by variations introduced in individual designs. Therefore, measurement difference in
binning circuit speed shall not be used for picking faster devices from devices of the same speed grade.
8/ This device is electrically compliant with the PCI Local Bus Specification Rev. 2.2.
9/ Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter
includes FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#,
PAR64, REQ64#, and ACK64#.
SIZE
STANDARD
5962-01515
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
E
SHEET
11
DSCC FORM 2234
APR 97
ACTEL [ Actel Corporation ]
