Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Status Word Settings
The Core1553BRT-EBR sets bits in the 1553EBR status word in compliance with MIL-STD-1553B. This is summarized in
Table 8.
Table 8 • Status Word Bit Settings
Bit(s)
Function
RT Address
Setting
15:11
Equals the RTADDR input
10
9
Message Error
Instrumentation
Service Request
Reserved
Set whenever the RT detects a message error
Always '0'
8
Controlled by the SSFLAG input
Always '000'
7:5
4
Broadcast Received
Busy
Set whenever a broadcast message is received
Controlled by the RTBUSY input
Controlled by the SSFLAG input
3
2
Sub-System Flag
1
Dynamic Bus Acceptance Always '0'. The Core1553BRT-EBR does not operate as a bus controller.
0
Terminal Flag
Controlled by the TFLAG input. If an "inhibit terminal flag" mode code is in effect, will be '0'.
As an example, the TSW address for a transmit command
with sub-address 24 would be '01111110100' (3F4h). The
TSW contains the information in Table 9 on page 14.
Command Word Storage
At the start of every 1553EBR bus transfer, the 1553EBR
command word is written to RAM locations 000–01F for
receive operations and 3E0–3FF for transmit operations.
The addresses are as follows:
If the RT is implemented without a memory-based
backend, the writing of the TSW can be disabled. This
simplifies the design of the backend logic that directly
controls backend functions.
CMD location RX commands: '000000' and SA
CMD location TX commands: '011111' and SA
If the RT is implemented without a memory-based
backend, the writing of the command word can be
disabled (WRTCMD input). This simplifies the design of
the backend logic that directly controls the backend
function.
Backend Access Times
During normal operation, the backend must allow a
memory access to complete within 1.0 µs.
While the status word is being transmitted, the core
must write the command word to memory and fetch the
first data word. Two memory accesses are performed in
the 2 µs that the status word takes to transmit.
Transfer Status Words (TSW)
At the end of every 1553EBR bus transfer, a transfer
status word is written to RAM in locations 000–01F for
receive operations and 3E0–3FF for transmit operations.
The addresses used are as follows:
At the end of
a
broadcast-receive command,
Core1553BRT-EBR writes the last data word and the TSW
value before the RT decodes the next command. Two
memory accesses occur in the 2 µs during which the
command word is being decoded.
TSW location RX commands: '000000' and SA
TSW location TX commands: '011111' and SA
The core includes a timer that is set to terminate
backend memory access at 1.0 µs.
Advanced v1.1
13
ACTEL [ Actel Corporation ]
