Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Table 7 • Standard Memory Address Map
Address
RAM Contents
Notes
000–01F
020–03F
RX transfer status words
Receive sub-address 1
…
The core only writes to these addresses (except
when SA30LOOP is high).
3C0–3DF
3E0–3FF
400–41F
420–43F
Receive sub-address 30
TX transfer status words
Not used
The core only reads from these addresses.
TX transfer sub-address 1
…
7C0–7DF
7E0–7FF
TX transfer sub-address 30
Not used
If the SA30LOOP input is set high, the RT maps transmit
sub-address 30 to the receive sub-address 30, i.e., the
upper address bit is forced to '0'. This provides a
loopback sub-address as per MIL-STD-1553EBR, Notice 2.
The TSW is still written to address 03EE. It should be
noted that this is not strictly compliant with the
specification since the transmit buffer will contain invalid
data if the received command fails, e.g., on a parity error.
The transmit buffer should only be updated if the receive
command had no errors. To implement this function in
full compliance with the specification, the SA30LOOP
input should be tied low, and the RT backend should
copy the receive memory buffer to the transmit memory
buffer only after the RT signals that the message was
received with no errors.
RX
Memory
Read
BUSAINEN
BUSAINP
BUSAINN
Write
Backend
Interface
TX
Memory
BUSAINH
BUSAOUTP
BUSAOUTN
Write
Read
BUSBINEN
BUSBINP
BUSBIN
When the memory buffer is implemented within the
FPGA device using dual-port RAMs, separate receive and
transmit RAM blocks can be used (each as 1 k words), as
shown in Figure 5. In these cases, the RX memory is
selected when A10 = 0 and the TX memory when
A10 = 1. In this case, the SA30LOOP input must be tied
low.
Command
Legality
Interface
Command
Legality
Block
BUSAINH
BUSBOUTP
BUSBOUTN
Core1553BRT-EBR
Figure 5 • Using Internal FPGA Memory Blocks
Advanced v1.1
11
ACTEL [ Actel Corporation ]
