ADDR1600C4G11
DDR3L-1600(CL11) 240-Pin R-DIMM
4GB(512M x 72-bits)
Pin Description：
PIN
NAME
FUNCTION
CK0~CK1,
/CK0~/CK1
System Clock
Clock Enable
Chip Select
Address
Active on the positive and negative edge to sample all inputs.
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at
least on cycle prior new command. Disable input buffers for power down in standby
CKE0~CKE1
/S0~/S1
Disables or Enables device operation by masking or enabling all input except CK, CKE and
L(U)DQM
Row / Column address are multiplexed on the same pins.
A0~A14
(Row Address: A0~A14 , Column Address: A0~A9 , Auto precharge: A10/AP)
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
BA0~BA2
Banks Select
Data
DQ0~DQ63
CB0~CB7
Data and check bit inputs / outputs are multiplexed on the same pins.
Bi-directional Data Strobe
DQS0~DQS8,
/DQS0~/DQS8
Data Strobe
DM0~DM8
/RAS
Data Mask
Mask input data when DM is high.
Row Address Strobe
Latches row addresses on the positive edge of the CK with /RAS low
/CAS
Column Address Strobe Latches Column addresses on the positive edge of the CK with /CAS low
/WE
Write Enable
Enables write operation and row recharge.
VDD / VSS
VREFDQ
VREFCA
VDDQ
Power Supply/Ground Power and Ground for the input buffers and the core logic.
Power Supply reference Power Supply for reference.DQ,DM.VDD/2
Power Supply reference Power Supply for reference. Command , address, & control.VDD/2
Power Supply
Serial data I/O
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity
EEPROM serial data I/O
SDA
7
ADATA [ ADATA Technology Co., Ltd. ]
