WS74HC595
Voltage waveforms 4. Pulse Durations
High-Level
Pulse 50%
t
w
V
cc
50%
0V
V
cc
Low-Level
Pulse
50%
50%
0V
Note
:
5. C
L
includes probe and test-fixture capacitance.
6. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by
generators having the following characteristics: PRR
≤
1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns.
7. For clock inputs, fmax is measured when the input duty cycle is 50%.
8. The outputs are measured one at a time, with one input transition per measurement.
9. tPLZ and tPHZ are the same as tdis.
10. tPZL and tPZH are the same as ten.
11. tPLH and tPHL are the same as tpd.
PIN DESCRIPTION
PIN NO.
SYMBOL
DESCRIPTION
15, 1, 2, 3, 4, 5, 6, 7
9
10
11, 12
13
14
8
16
Q
1
– Q
8
Q
8’
SRCL
SRCK, RCK
OE
SER
GND
V
CC
Parallel data outputs
Serial data output
Shift register reset input (active low)
Shift and storage register clock inputs
(triggered at positive edge)
Output enable input (active low)
Serial data input
Ground (0V)
Positive power supply
11
SRCK
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
1
16
V
cc
Q
1
SER
OE
RCK
12
RCK
9
Q
8’
15
Q
1
Q
2
1
2
Q
3
3
Q
4
4
Q
5
5
Q
6
6
Q
7
Q
8
7
OE
14
SER
SRCK
Q
8
SRCL
8
9
SRCL
GND
Q
8’
10
13
Pin Configuration
Logic Symbol
7
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