W19B(L)320ST/B
8.4.8 Alternate #CE Controlled Erase and Program Operations
90 nS
UNIT
PARAMETER
SYM.
TYP.
MAX.
MIN.
(Note3)
(Note4)
Write Cycle Time (Note 1)
TWC
TAS
TAH
TDS
TDH
90
0
45
45
0
-
-
-
-
-
-
-
-
-
-
nS
nS
nS
nS
nS
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Recover Time Before Write (#OE High to #WE
Low)
TGHEL
0
-
-
nS
#WE Setup Time
#WE Hold Time
#CE Pulse Width
#CE Pulse Width High
TWS
TWH
TCP
TCPH
TPB
0
0
35
30
-
-
-
-
-
5
7
-
-
-
nS
nS
nS
nS
-
Byte
150
210
Programming Time (Note 6)
Word
Byte
Accelerated Programming Time (Note 6)
Word
µS
µS
TPW
-
TACCP
-
4
120
Sector Erase Time (Note 2)
Chip Erase Time (Note 2)
TSE
TCE
TCPB
TCPW
-
-
-
-
0.7
49
21
14
15
-
63
42
Sec
Sec
Byte
Chip Program Time (Note 5)
Word
Sec
Notes:
1. Not 100 % tested.
2. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
3. Typical program and erase time assume the following conditions :25°C, 3.0 V VDD, 10,000 or 100,000
cycles .Additionally, programming typicals assume checkerboard pattern.
4. Under worst case conditions of 90°C, VDD = 2.7V for W19B320S or VDD = 3.0V for W19L320S, 10,000 or 100,000
cycles.
5. The typical chip programming time is considerably less than the maximun chip programming time listed,since most
bytes program faster than maximun program times listed.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
7. The device has a minimum erase and program cycle endurance of 10,000 or100,000 cycles.
Publication Release Date: March 23, 2004
- 41 -
Revision A2
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